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IS24C16
IS24C16
16,384-BIT SERIAL ELECTRICALLY
ERASABLE PROM
ISISSSII
ADVANCE INFORMATION
OCTOBER 1997
OVERVIEW
FEATURES
The IS24C16 is a low cost, low power, low voltage
serial EEPROM and organized as 2,048 x 8 bits. The
memory is configured as 128 pages of 16 bytes each. It is
fabricated using ISSI’s advanced CMOS EEPROM tech-
nology and operates from a single supply.
• Low power CMOS
– Active current less than 3.0 mA
– Standby current less than 35 µA
• Hardware write protection
– Write control pin
The IS24C16 is internally organized as a 256 x 8 memory
bank. The IS24C16 features a serial interface and soft-
ware protocol allowing operation on a simple 2-wire bus.
Included is a bidirectional serial data bus synchronized by
a clock offering flexible byte write and a faster 16-byte
pagewrite.Awriteprotectpincanprotectdataintheupper
quadrant of memory.
• Internally organized as eight banks
– 256 pages x 8 bytes
• Two-wire serial interface
— Bidirectional data transfer protocol
• Flexible byte write and 16-byte page-write
modes
• High-reliability
– Endurance: 100,000 cycles per byte
– Data retention: 100 years
• Automatic word address incrementing
— Sequential register read
• Filtered inputs for noise suppression
• 8-pin PDIP or SOIC packages
PIN CONFIGURATION
8-Pin DIP and SOIC
PIN DESCRIPTIONS
SerialClock(SCL)-TheSCLinputisusedtoclockalldata
into and out of the device. In the WRITE mode, data must
remainstablewhenSCLisHIGH. IntheREADmode, data
is clocked out on the falling edge of SCL.
A0
A1
1
2
3
4
8
7
6
5
VCC
WC
SerialData(SDA)-TheSDApinisabidirectionalpinused
to transfer data into and out of the device. Data may
change only when SCL is LOW. It is an open-drain output,
and may be wire-ORed with any number of open-drain or
open-collector outputs.
A2
SCL
SDA
GND
PIN DESCRIPTIONS
A0, A1, and A2: These pins are not connected.
A0-A2
SDA
SCL
WC
Address Inputs (No connection)
Serial Data I/O
Serial Clock Input
Write Control Input
Power
Write Control (WC) - The Write Control input is used to
disable any attempt to write to the memory. When HIGH,
the upper half of array is protected against write opera-
tions;whenLOW,thewritefunctionisnormal.Thepartcan
be read independent of the state of WC pin. When not
connected this pin will be pulled LOW.
Vcc
GND
Ground
This document contains ADVANCE INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible
product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1997, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION EE001-0C
1
10/03/97