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IMISG571DYB PDF预览

IMISG571DYB

更新时间: 2024-10-27 23:58:39
品牌 Logo 应用领域
其他 - ETC 时钟发生器外围集成电路光电二极管
页数 文件大小 规格书
15页 224K
描述
CPU System Clock Generator

IMISG571DYB 数据手册

 浏览型号IMISG571DYB的Datasheet PDF文件第2页浏览型号IMISG571DYB的Datasheet PDF文件第3页浏览型号IMISG571DYB的Datasheet PDF文件第4页浏览型号IMISG571DYB的Datasheet PDF文件第6页浏览型号IMISG571DYB的Datasheet PDF文件第7页浏览型号IMISG571DYB的Datasheet PDF文件第8页 
SG571D  
I2C Frequency Clock Generator w/ EMI Reduction Spread Spectrum Technology  
for Pentium Processor Based Designs.  
Approved Product  
SERIAL CONTROL REGISTERS (Cont.)  
Function Table  
Function  
Description  
Tri-State  
Test Mode  
Normal SEL=1  
Normal SEL=0  
Outputs  
Ref  
Hi-Z  
Tclk  
14.318  
14.318  
CPU  
Hi-Z  
Tclk/2  
66  
PCI  
Hi-Z  
Tclk/4  
CPU/2  
CPU/2  
SDRAM  
Hi-Z  
Tclk/2  
CPU  
IOAPIC  
Hi-Z  
Tclk  
14.318  
14.318  
24MHZ  
Hi-Z  
Tclk/4  
24  
48MHZ  
Hi-Z  
Tclk/2  
48  
60  
CPU  
24  
48  
Notes:  
1. Tclk is a test clock over driven on the Xin input during test mode.  
2. The frequency ratio Fout/Fin for the USB output is 3.35294.  
Byte 1: CPU, 48/24 MHz Clock Register (1 = enable, 0 = Stopped)  
Bit  
7
6
5
4
@Pup  
Pin#  
23  
22  
-
-
39  
Description  
1
1
x
x
1
48/24 MHz enable/Stopped  
48/24 MHz enable/Stopped  
Reserved  
Reserved  
Power Control for CPUMCLK1  
3,2  
Bit 2  
Bit 3  
0
1
0
1
0
0
1
1
= Disabled  
= Not Allowed  
= Not Allowed  
= High Drive  
1
0
1
1
41  
42  
CPUCLK enable/Stopped  
CPUMCLK0 enable/Stopped  
Byte 2: PCI Clock Register (1 = enable, 0 = Stopped)  
Bit  
7
6
5
4
3
2
1
0
@Pup  
Pin#  
-
8
16  
14  
13  
12  
11  
9
Description  
Reserved  
x
1
1
1
1
1
1
1
PCICLK_F enable/Stopped  
PCICLK5 enable/Stopped  
PCICLK4 enable/Stopped  
PCICLK3 enable/Stopped  
PCICLK2 enable/Stopped  
PCICLK1 enable/Stopped  
PCICLK0 enable/Stopped  
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.  
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571  
Rev.1.4  
8/10/98  
Page 5 of 15  

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