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IMISG571DYB PDF预览

IMISG571DYB

更新时间: 2024-10-27 23:58:39
品牌 Logo 应用领域
其他 - ETC 时钟发生器外围集成电路光电二极管
页数 文件大小 规格书
15页 224K
描述
CPU System Clock Generator

IMISG571DYB 数据手册

 浏览型号IMISG571DYB的Datasheet PDF文件第1页浏览型号IMISG571DYB的Datasheet PDF文件第2页浏览型号IMISG571DYB的Datasheet PDF文件第3页浏览型号IMISG571DYB的Datasheet PDF文件第5页浏览型号IMISG571DYB的Datasheet PDF文件第6页浏览型号IMISG571DYB的Datasheet PDF文件第7页 
SG571D  
I2C Frequency Clock Generator w/ EMI Reduction Spread Spectrum Technology  
for Pentium Processor Based Designs.  
Approved Product  
2-WIRE I2C CONTROL INTERFACE  
The 2-wire control interface implements a write only slave interface. The IMISG571D cannot be read back. Sub-  
addressing is not supported, thus all preceding bytes must be sent in order to change one of the control bytes. The 2-  
wire control interface allows each clock output to be individually enabled or disabled. It also allows 24/48 MHZ frequency  
selection and test mode enable.  
During normal data transfer, the SDATA signal only changes when the SDCLK signal is low, and is stable when  
SDCLK is high. There are two exceptions to this. A high to low transition on SDATA while SDCLK is high is used to  
indicate the start of a data transfer cycle. A low to high transition on SDATA while SDCLK is high indicates the end of a  
data transfer cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated. The first  
byte of a transfer cycle is a 7-bit address with a Read/Write bit as the LSB. Data is transferred MSB first.  
The device will respond to writes to 10 bytes (max) of data to address D2 by generating the acknowledge (low)  
signal on the SDATA wire following reception of each byte. The device will not respond to any other control interface  
conditions. The I2C interface is disabled when the PWR_DWN# pin is low. Previously set control registers are retained.  
SERIAL CONTROL REGISTERS  
NOTE: The Pin# column lists the affected pin number where applicable. The @Pup column gives the state at true  
power up. Bytes are set to the values shown only on true power up, and not when the PWR_DWN# pin is activated.  
Following the acknowledge of the Address Byte (D2), two additional bytes must be sent:  
1) “Command Code “ byte, and  
2) “Byte Count” byte.  
Although the data (bits) in these two bytes are considered “don’t care”, they must be sent and will be acknowledged.  
Byte 0: Function Select Register  
Bit  
7
6
5
4
3
2
1
0
@Pup  
Pin#  
*
*
*
*
Description  
Reserved  
Reserved  
Reserved  
0
0
0
0
1
1
0
0
Reserved  
23  
22  
48/24 Mhz (a”1” sets the output to 48MHz, a “0” sets the output to 24MHz)  
48/24 Mhz (a”1” sets the output to 48MHz, a “0” sets the output to 24MHz)  
Bit1 Bit0  
1
1
0
0
1 Tri-State  
0 Spread Spectrum operating mode  
1 Test Mode  
0
Normal operating mode  
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.  
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571  
Rev.1.4  
8/10/98  
Page 4 of 15  

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