Datasheet > IMISG571DYB

IMISG571DYB

更新时间： 2024-01-20 15:27:19

品牌	Logo	应用领域
其他 - ETC		时钟发生器外围集成电路光电二极管
页数	文件大小	规格书
15页	224K
描述
CPU System Clock Generator

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技术参数
数据手册

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IMISG571DYB 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	包装说明：	SSOP-48
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.88
Is Samacsys：	N	JESD-30 代码：	R-PDSO-G48
JESD-609代码：	e0	长度：	15.875 mm
湿度敏感等级：	1	端子数量：	48
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	SSOP
封装等效代码：	SSOP48,.4	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, SHRINK PITCH	峰值回流温度（摄氏度）：	220
电源：	2.5,3.3 V	认证状态：	Not Qualified
座面最大高度：	2.794 mm	子类别：	Clock Generators
最大压摆率：	100 mA	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.635 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	7.5 mm
uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER	Base Number Matches：	1

IMISG571DYB 数据手册

SG571D

I²C Frequency Clock Generator w/ EMI Reduction Spread Spectrum Technology

for Pentium Processor Based Designs.

Approved Product

2-WIRE I²C CONTROL INTERFACE

The 2-wire control interface implements a write only slave interface. The IMISG571D cannot be read back. Sub-

addressing is not supported, thus all preceding bytes must be sent in order to change one of the control bytes. The 2-

wire control interface allows each clock output to be individually enabled or disabled. It also allows 24/48 MHZ frequency

selection and test mode enable.

During normal data transfer, the SDATA signal only changes when the SDCLK signal is low, and is stable when

SDCLK is high. There are two exceptions to this. A high to low transition on SDATA while SDCLK is high is used to

indicate the start of a data transfer cycle. A low to high transition on SDATA while SDCLK is high indicates the end of a

data transfer cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated. The first

byte of a transfer cycle is a 7-bit address with a Read/Write bit as the LSB. Data is transferred MSB first.

The device will respond to writes to 10 bytes (max) of data to address D2 by generating the acknowledge (low)

signal on the SDATA wire following reception of each byte. The device will not respond to any other control interface

conditions. The I²C interface is disabled when the PWR_DWN# pin is low. Previously set control registers are retained.

SERIAL CONTROL REGISTERS

NOTE: The Pin# column lists the affected pin number where applicable. The @Pup column gives the state at true

power up. Bytes are set to the values shown only on true power up, and not when the PWR_DWN# pin is activated.

Following the acknowledge of the Address Byte (D2), two additional bytes must be sent:

1) “Command Code “ byte, and

2) “Byte Count” byte.

Although the data (bits) in these two bytes are considered “don’t care”, they must be sent and will be acknowledged.

Byte 0: Function Select Register

Bit

@Pup

Pin#

Description

Reserved

48/24 Mhz (a”1” sets the output to 48MHz, a “0” sets the output to 24MHz)

Bit1 Bit0

1 Tri-State

0 Spread Spectrum operating mode

1 Test Mode

Normal operating mode

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.

MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571

Rev.1.4

8/10/98

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与IMISG571DYB相关器件

型号	品牌	获取价格	描述	数据表
IMISG572AYB	CYPRESS	获取价格	Processor Specific Clock Generator, 100MHz, CMOS, PDSO48, SSOP-48
IMISG577CYB	ETC	获取价格	CPU System Clock Generator
IMISG577DYB	CYPRESS	获取价格	Processor Specific Clock Generator, CMOS, PDSO48
IMISG579BYB	CYPRESS	获取价格	Clock Generator, PDSO56,
IMISG587DTB	CYPRESS	获取价格	Video Clock Generator, CMOS, PDSO8, TSSOP-8
IMISG742AYB	CYPRESS	获取价格	Clock Generator, PDSO48,
IMISG745BYB	ETC	获取价格	CPU System Clock Generator
IMISG748CYB	ETC	获取价格	CPU System Clock Generator
IMISG750CYB	ETC	获取价格	CPU System Clock Generator
IMISM530ATB	CYPRESS	获取价格	Processor Specific Clock Generator, 120MHz, CMOS, PDSO20, TSSOP-20

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