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IMISG577DYB PDF预览

IMISG577DYB

更新时间: 2024-01-26 21:21:17
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 光电二极管外围集成电路
页数 文件大小 规格书
11页 230K
描述
Processor Specific Clock Generator, CMOS, PDSO48

IMISG577DYB 技术参数

生命周期:Transferred包装说明:,
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.51
JESD-30 代码:R-PDSO-G48端子数量:48
封装主体材料:PLASTIC/EPOXY封装形状:RECTANGULAR
封装形式:SMALL OUTLINE认证状态:Not Qualified
表面贴装:YES技术:CMOS
端子形式:GULL WING端子位置:DUAL
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches:1

IMISG577DYB 数据手册

 浏览型号IMISG577DYB的Datasheet PDF文件第2页浏览型号IMISG577DYB的Datasheet PDF文件第3页浏览型号IMISG577DYB的Datasheet PDF文件第4页浏览型号IMISG577DYB的Datasheet PDF文件第5页浏览型号IMISG577DYB的Datasheet PDF文件第6页浏览型号IMISG577DYB的Datasheet PDF文件第7页 
SG577D  
LOW EMI Clock Generator for Pentium II Systems with Power  
Management  
Features  
Frequency Table  
• Supports Pentium® and Pentium® II CPUs  
• Designed to meet Intel chipset specification  
• Four CPU and eight PCI clocks  
• Two 48-MHz fixed clocks for USB and Super IO  
• Separate supply pins for mixed CPU, IOAPIC, and  
Fixed/PCI clocks  
• < 175 ps max. skew among CPU clocks  
• < 250 ps max. skew among PCI clocks  
• Controlled current output buffers  
• Power management feature  
• Two IOAPIC clocks for multiprocessor support  
• 48-pin SSOP package  
FS2 FS1  
FS0  
0
CPU  
3-state  
PCI  
3-state  
33.3  
0
0
1
0
1
0
1
1
66 (66.58)[1]  
0
Ref/2  
Ref/4  
33.2[2]  
1
1
100 (99.7)[2]  
Notes:  
1. Down Spread 1.25% (total).  
2. Down Spread 0.5% (total).  
• Spread Spectrum EMI reduction mode  
Block Diagram  
Connection Diagram  
XIN  
VDD  
REF1  
REF2  
VSS  
XIN  
XOUT  
VSS  
1
2
3
4
5
6
7
8
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
VDDR  
REF3  
VDDI  
IOAPIC1  
IOAPIC2  
VSS  
30pF  
30pF  
XB  
UF  
REF1  
1
300K  
XOUT  
VDD  
VDDI  
VDDC  
VDD  
VDD  
REF0  
IOAPIC  
CPU(0:1)  
PCI(1:5)  
PCI_F  
1
1
PCI_F  
PCI1  
VDDP  
PCI2  
PCI3  
VSS  
PCI4  
PCI5  
VDDP  
PCI6  
PCI7  
VSS  
VDD  
VSS  
VDDF  
48M1  
48M2  
VSS  
N/C  
VDDC  
CPU1  
CPU2  
VSS  
VDDC  
CPU3  
CPU4  
VSS  
VDD  
VSS  
PSTOP  
CSTOP  
PD  
9
PLL1  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
cpu  
2
Rin  
5
1
pci  
S3  
Latch  
S2  
S1  
S0  
VDDS  
VDDS  
Mode  
SDRAM10  
1
1
SSM  
FS0  
FS1  
FS2  
I2CPMU  
SDRAM11  
PS#  
CS#  
SCLK  
SDATA  
C
D
VDDS  
VDD  
SDRAM(0:9,12,13)  
48MHZ  
CLKIN  
12  
1
Rin  
48  
24  
PLL2  
VDD  
24MHZ  
1
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-07194 Rev. **  
Revised December 6, 2001  

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