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IMIZ9104DAB PDF预览

IMIZ9104DAB

更新时间: 2024-02-14 03:51:52
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 驱动逻辑集成电路
页数 文件大小 规格书
7页 119K
描述
PLL Based Clock Driver, 6 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1 MM HEIGHT, PLASTIC, TQFP-32

IMIZ9104DAB 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:7 X 7 MM, 1 MM HEIGHT, PLASTIC, TQFP-32
针数:32Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.85
输入调节:STANDARDJESD-30 代码:S-PQFP-G32
JESD-609代码:e0长度:7 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER最大I(ol):0.02 A
功能数量:1反相输出次数:
端子数量:32实输出次数:6
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TQFP封装等效代码:TQFP32,.35SQ,32
封装形状:SQUARE封装形式:FLATPACK, THIN PROFILE
峰值回流温度(摄氏度):240电源:2.5,3.3 V
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.6 ns
座面最大高度:1.2 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:7 mm最小 fmax:30 MHz
Base Number Matches:1

IMIZ9104DAB 数据手册

 浏览型号IMIZ9104DAB的Datasheet PDF文件第2页浏览型号IMIZ9104DAB的Datasheet PDF文件第3页浏览型号IMIZ9104DAB的Datasheet PDF文件第4页浏览型号IMIZ9104DAB的Datasheet PDF文件第5页浏览型号IMIZ9104DAB的Datasheet PDF文件第6页浏览型号IMIZ9104DAB的Datasheet PDF文件第7页 
Z9104  
Variable Delay Motherboard Clock Buffer  
Table 1. Feedback Scale Select Codes  
Features  
Mode FBS1 FBS0 Pcounter  
Ncounter  
³ 8  
MF[1]  
2.0  
• Outputphaserelationshipispreciselycontrollablewith  
respecttoinputclockviaadedicatedexternalfeedback  
path  
• Two-kV ESD protected  
• Six low-skew clocks generated  
• One 2.5V output clock  
• Outputs are individually enabled  
• Output frequencies from 30 to 120 MHz  
• 3.3V power supply  
• Synchronous output enable and disable control  
• 45–55% output duty cycle  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
³ 4  
³ 4  
³ 4  
³ 8  
³ 4  
³ 4  
³ 4  
³ 8  
³ 10  
³ 12  
³ 12  
³ 4  
2.5  
3.0  
1.5  
1.0  
³ 5  
1.25  
1.5  
³ 6  
• ±100 ps cycle-to-cycle jitter  
• 32-lead TQFP package  
³ 8  
1.0  
Note:  
1. Multiplication Factor The multiplication factor for these configurations is  
the output frequency with respect to REFIN (FOUT = FIN × multiplication  
factor).  
• Pin-compatible with MPC932P  
Block Diagram  
Pin Configuration  
MODE  
FBS0  
FBS1  
VDDF  
Ncounter  
FBOUT  
FBIN  
REFIN  
PLL  
1
0
Pcounter  
PLLEN  
VDDI  
REFIN  
PLLEN  
FBS0  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
VSS  
CLK3  
VDD  
CLK4  
Stop  
Logic  
CLK25  
SC25  
VDD25  
FBS1  
Z9104 20 VSS  
CLK2  
CLK3  
CLK4  
OEALL  
STOPCLK  
VSSI  
19  
18  
17  
CLK5  
VDD  
CLK6  
Stop  
Logic  
SC2,3  
Stop  
SC4  
SC5  
SC6  
Logic  
CLK5  
CLK6  
Stop  
Logic  
Stop  
Logic  
VDD  
STOPCLK  
OEALL  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-07083 Rev. *C  
Revised May 6, 2002  

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