Datasheet > IMK2-67025V-25

IMK2-67025V-25

更新时间： 2024-10-28 15:35:11

品牌	Logo	应用领域
爱特美尔 - ATMEL		静态存储器内存集成电路
页数	文件大小	规格书
23页	257K
描述
Dual-Port SRAM, 8KX16, 25ns, CMOS, PQFP84, 0.050 INCH, MQFP-84

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IMK2-67025V-25 数据手册

MATRA MHS

M 67025

8 K × 16 CMOS Dual Port RAM

Introduction

The M 67025 is a very low power CMOS dual port static Using an array of eigh transistors (8T) memory cell and

RAM organised as 8192 × 16. The M 67025 is designed fabricated with the state of the art 0.65 µ lithography

to be used as a stand-alone 16 bit dual port RAM or as a named SCMOS, the M 67025 combines an extremely low

combination MASTER/SLAVE dual port for 32 bit or standby supply current (typ = 1.0 µA) with a fast access

width

systems.

The

MATRA-MHS time at 20 ns over the full temperature range. All versions

MASTER/SLAVE dual port approach in memory system offer battery backup data retention capability with a

applications results in full speed, error free operation typical power consumption at less than 5 µW.

without the need of an additional discrete logic.

For military/space applications that demand superior

Master and slave devices provide two independant ports

with separate control, address and I/O pins that permit

independant, asynchronous access for reads and writes to

any location in the memory. An automatic power down

feature controlled by CS permits the on-chip circuitry of

each port in order to enter a very low stand by power

mode.

levels of performance and reliability the M 67025 is

processed according to the methods of the latest revision

of the MIL STD 883 (class B or S) and/or ESA SCC 9000.

Features

D Fast access time : 20/25/30/35/45/55 ns

D Wide temperature range :

D Versatile pin select for master or slave :

– M/S = H for busy output flag on master

– M/S = L for busy input flag on slave

–55 °C to +125 °C

D 67025 L low power

D INT flag for port to port communication

D Full hardware support of semaphore signaling between ports

D Fully asynchronous operation from either port

D Battery back-up operation : 2 V data retention

D TTL compatible

67025 V very low power

D Separate upper byte and lower byte control for multiplexed

bus compatibility

D Expandable data bus to 32 bits or more using master/slave

chip select when using more than one device

D On chip arbitration logic

D Single 5 V ± 10 % power supply

D For 3.3 V version, please consult sales

Rev. D (29/09/95)

12 3 4 5 6 7...23

中文翻译

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与IMK2-67025V-25相关器件

型号	品牌	获取价格	描述	数据表
IMK2-67025V-30	TEMIC	获取价格	Dual-Port SRAM, 8KX16, 30ns, CMOS, PQFP84, 0.050 INCH, MQFP-84
IMK2-67025V-35	TEMIC	获取价格	Dual-Port SRAM, 8KX16, 35ns, CMOS, PQFP84, 0.050 INCH, MQFP-84
IMK2-67025V-55	TEMIC	获取价格	Dual-Port SRAM, 8KX16, 55ns, CMOS, PQFP84, 0.050 INCH, MQFP-84
IMKK-67130L-35:D	TEMIC	获取价格	Dual-Port SRAM, 1KX8, 35ns, CMOS, CQFP48,
IMKK-67130L-35:RD	TEMIC	获取价格	Dual-Port SRAM, 1KX8, 35ns, CMOS, CQFP48,
IMKK-67130L-35SHXXX:R	TEMIC	获取价格	Dual-Port SRAM, 1KX8, 35ns, CMOS, CQFP48,
IMKK-67130L-35SHXXX:RD	TEMIC	获取价格	Dual-Port SRAM, 1KX8, 35ns, CMOS, CQFP48,
IMKK-67130L-45	TEMIC	获取价格	Dual-Port SRAM, 1KX8, 45ns, CMOS, CQFP48,
IMKK-67130L-45SHXXX:RD	TEMIC	获取价格	Dual-Port SRAM, 1KX8, 45ns, CMOS, CQFP48,
IMKK-67130L-55	TEMIC	获取价格	Dual-Port SRAM, 1KX8, 55ns, CMOS, CQFP48,

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