Datasheet > IMIZ9972BAT

IMIZ9972BAT

更新时间： 2024-10-27 22:05:07

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
9页	90K
描述
3.3V, 125-MHz, Multi-Output Zero Delay Buffer

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替代型号

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IMIZ9972BAT 数据手册

Z9972

3.3V, 125-MHz, Multi-Output Zero Delay Buffer

Table 1. Frequency Table^[1]

Features

VCO_SEL FB_SEL2 FB_SEL1 FB_SEL0

F_VCO

• Output frequency up to 125 MHz

• 12 clock outputs: frequency configurable

• 350 ps max output-to-output skew

• Configurable output disable

• Two reference clock inputs for dynamic toggling

• Oscillator or crystal reference input

• Spread Spectrum-compatible

• Glitch-free output clocks transitioning

• 3.3V power supply

• Pin-compatible with MPC972

12x

16x

20x

16x

24x

32x

40x

• Industrial temperature range: –40°C to +85°C

• 52-pin TQFP package

10x

12x

16x

20x

Note:

1. x = the reference input frequency, 200 MHz < F_VCO< 480 MHz.

Block Diagram

Pin Configuration

XIN

XOUT

VCO_SEL

PLL_EN

REF_SEL

Sync

Frz

QA0

QA1

QA2

QA3

Phase

Detector

VCO

TCLK0

TCLK1

LPF

TCLK_SEL

52 51 50 49 48 47 46 45 44 43 42 41 40

FB_IN

VSS

MR#/OE

SCLK

Sync

Frz

QB0

QB1

VDDC

QB1

SDATA

FB_SEL2

PLL_EN

REF_SEL

TCLK_SEL

TCLK0

QB2

QB3

FB_SEL2

VSS

QB2

VDDC

QB3

Z9972

MR#/OE

Sync

Frz

QC0

QC1

Power-On

Reset

FB_IN

VSS

/4, /6, /8, /12

/4, /6, /8, /10

/2, /4, /6, /8

TCLK1

Sync

Frz

QC2

SELA(0,1)

FB_OUT

VDDC

FB_SEL0

XIN

XOUT

QC3

SELB(0,1)

SELC(0,1)

Sync

Frz

VDD

FB_OUT

/4, /6, /8, /10

Sync Pulse

14 15 16 17 18 19 20 21 22 23 24 25 26

Sync

Frz

SYNC

FB_SEL(0,1)

Data Generator

SCLK

Output Disable

Circuitry

SDATA

INV_CLK

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-07088 Rev. *D

Revised December 21, 2002

12 3 4 5 6 7...9

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IMIZ9972BAT 替代型号

型号	品牌	替代类型	描述	数据表
IMIZ9972BA	CYPRESS	类似代替	3.3V, 125-MHz, Multi-Output Zero Delay Buffer

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IMIZ9974	ETC	获取价格	Clocks and Buffers
IMIZ9974CA	CYPRESS	获取价格	3.3V, 125-MHz, Multi-Output Zero Delay Buffer
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