Datasheet > IMISG577DYB

IMISG577DYB

更新时间： 2024-02-06 17:40:50

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		光电二极管外围集成电路
页数	文件大小	规格书
11页	230K
描述
Processor Specific Clock Generator, CMOS, PDSO48

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中文翻译

获取价格

技术参数
数据手册

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IMISG577DYB 技术参数

生命周期：	Transferred	包装说明：	,
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.51
JESD-30 代码：	R-PDSO-G48	端子数量：	48
封装主体材料：	PLASTIC/EPOXY	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	认证状态：	Not Qualified
表面贴装：	YES	技术：	CMOS
端子形式：	GULL WING	端子位置：	DUAL
uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, PROCESSOR SPECIFIC	Base Number Matches：	1

IMISG577DYB 数据手册

SG577D

power up, (after bring PD from a low to high state) the VCOs

will stabilize to the correct pulse widths within about 0.2 mS.

The CPU and PCI clocks transition between running and

stopped by waiting for one positive edge on PCI_F followed by

a negative edge on the clock of interest, after which high levels

of the output are either enabled or disabled.

Power Management Functions

All PCI (excluding PCI_F) and CPU clocks can be enabled or

stopped via the PSTOP and CSTOP input pins. All clocks are

stopped in the low state. All clocks maintain a valid high period

on transitions from running to stopped and on transitions from

stopped to running when the chip was not powered down. On

CSTOP

PSTOP

CPUCLK

LOW

PCICLK

LOW

OTHER CLKs

LOW

XTAL and VCOs

OFF

LOW

RUNNING

LOW

RUNNING

LOW

RUNNING

Power Management Timing

PCICLK_F

PSTOP

PCICLK(0:5)

CSTOP

CPUCLK(0:3)

Power Management Timing

Latency

Signal

Signal State

Number of Rising Edges of Free-Running PCICLK (PCIF)

CSTOP

PSTOP

0 (disabled)

1 (enabled)

0 (disabled)

1 (enabled)

1 (normal operation)

0 (power down)

3 mS

2 mS max.

Notes:

4. Clock n/off latency is defined in the number of rising edges of free running PCICLKs between the clock disable goes LOW/HIGH to the first valid clock

comes out of the device.

5. Power-up latency is when PWR_DWN # goes inactive (HIGH) to when the first valid clocks are driven from the device.

Document #: 38-07194 Rev. **

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