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IMISG587DTB PDF预览

IMISG587DTB

更新时间: 2024-01-25 05:42:38
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
6页 57K
描述
Video Clock Generator, CMOS, PDSO8, TSSOP-8

IMISG587DTB 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:TSSOP, TSSOP8,.25
针数:8Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.92JESD-30 代码:R-PDSO-G8
JESD-609代码:e0长度:4.4 mm
端子数量:8最高工作温度:70 °C
最低工作温度:最大输出时钟频率:17.7344 MHz
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 V主时钟/晶体标称频率:14.31818 MHz
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Clock Generators最大压摆率:11 mA
最大供电电压:3.63 V最小供电电压:2.97 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, VIDEOBase Number Matches:1

IMISG587DTB 数据手册

 浏览型号IMISG587DTB的Datasheet PDF文件第2页浏览型号IMISG587DTB的Datasheet PDF文件第3页浏览型号IMISG587DTB的Datasheet PDF文件第4页浏览型号IMISG587DTB的Datasheet PDF文件第5页浏览型号IMISG587DTB的Datasheet PDF文件第6页 
SG587  
Programmable NTSC/PAL Clock Generator  
Product Features  
Pin Description  
The IMISG587 is a clock generator that generates  
17.734MHz using Phase Locked Loops (PLLs). The  
IMISG587 uses a 14.318MHz crystal to produce  
NTSC or PAL frequencies. The device is packaged in  
an 8pin TSSOP package for minimum occupation of  
board space.  
XIN, XOUT - Forms an on-chip reference oscillator  
when connected to terminals of an external parallel  
resonant crystal, 14.318MHz. XIN may also serve as  
input for an externally generated reference signal.  
CLK1 – CLK1 is derived from the reference crystal  
oscillator by using Phase-Locked Loop (PLL) or  
buffered reference output selected via NT/PAL input  
pin.  
Convert/buffered  
14.318MHz crystal.  
Fsc  
frequency  
using  
Internal Loop Filter that requires no external  
components or adjustments.  
30 mA buffer switching current  
8 pin TSSOP package.  
CLK2 – CLK2 provides the required NTSC or PAL  
clock frequencies. This is obtained by dividing the  
CLK1 frequency by four (4).  
NT/PAL – This pin is used to select NTSC or PAL  
frequency. When High (default), CLK1 to be selected  
crystal frequency, 14.318MHz. When Low, CLK1 to  
be selected PAL frequencies, 17.734MHz, through  
PLL circuit. See table-1. This pin has an internal pull-  
up resister.  
Pin Configuration  
CLK2ON – This pin is used to enable/disable CLK2  
output. When Low, CLK2 to be disabled. When High  
(default), CLK2 to be enabled. This pin has an  
internal pull-up resister.  
1
2
NT/PAL  
VSS  
8 CLK2ON  
PLL  
CLK2  
VDD  
7
6
1/4  
MPX  
XIN  
3
4
VDD – Circuit positive power supply.  
VSS – Circuit ground.  
X'tal  
Osc.  
XOUT  
5 CLK1  
Cypress Semiconductor Corporation  
3901 North First Sreet  
Document#: 38-07102 Rev. **  
9/15/2000  
San Jose, CA 95134 Tel 408-943-2600  
Page 1 of 6  

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