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IMISG571DYB PDF预览

IMISG571DYB

更新时间： 2024-02-15 20:14:46
品牌 Logo 应用领域
其他 - ETC 时钟发生器外围集成电路光电二极管
页数 文件大小 规格书
15页 224K
描述
CPU System Clock Generator

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IMISG571DYB 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete包装说明：SSOP-48
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.88
Is Samacsys：NJESD-30 代码：R-PDSO-G48
JESD-609代码：e0长度：15.875 mm
湿度敏感等级：1端子数量：48
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装等效代码：SSOP48,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH峰值回流温度（摄氏度）：220
电源：2.5,3.3 V认证状态：Not Qualified
座面最大高度：2.794 mm子类别：Clock Generators
最大压摆率：100 mA表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7.5 mm
uPs/uCs/外围集成电路类型：CLOCK GENERATOR, OTHERBase Number Matches：1

IMISG571DYB 数据手册

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SG571D  
I2C Frequency Clock Generator w/ EMI Reduction Spread Spectrum Technology  
for Pentium Processor Based Designs.  
Approved Product  
PIN DESCRIPTION  
Xin, Xout - These pins form an on-chip reference oscillator  
when connected to terminals of an external parallel resonant  
crystal (nominally 14.318 MHz). Xin may also serve as input  
for an externally generated reference signal.  
PCICLK_F - A PCI clock output that does not stop until in  
power down mode. It is synchronous with other PCI clocks.  
REF(0:2) - Buffered outputs of on-chip reference.  
SEL - Standard frequency select input. It has internal pull-up.  
IOAPIC0 - Buffered output of 14.3MHZ for multiprocessor  
support. It is powered by Vddq2.  
CPUCLK - Hose clock output primarily use to drive the  
SDRAM.  
PWR_DWN# - Power down pin. When this pin is asserted  
low, the IC is in shutdown mode where all circuitry is turned  
off including VCO, crystal buffer and PCICLK_F. It has an  
internal pull-up. The I2C interface is disabled with the  
PWR_DWN# pin is low.  
CPUMCLK(0:1) - High drive host clock output primarily used  
to drive Mobil Pentium processor modules.  
SDRAM(0:5) - Synchronous DRAM DIMs clocks. They are  
powered by Vddq3.  
48/24MHz(0:1) - Programmable 48 MHZ or 24 MHZ clock  
outputs.  
SDRAM6/CPU_STOP#  
-
If MODE=1, this pin is  
a
SDATA - serial data of I2C 2-wire control interface. Has  
internal pull-up resistor.  
Synchronous DRAM DIMs clock output. If MODE=0, this pin  
is a CPU_STOP# input signal, where a low level stops the  
CPU however, the SDRAM clocks will stay active. It has an  
internal pull-up.  
SDCLK - serial clock of I2C 2-wire control interface. Has  
internal pull-up resistor.  
SDRAM7/PCI_STOP#  
-
If MODE=1, this pin is  
a
Vss - Ground pins for the chip.  
Synchronous DRAM DIMs clock output. If MODE=0, this pin  
is a PCI_STOP# input signal, where a low level stops the PCI  
clocks. It has an internal pull-up.  
Vdd - 3.3 Volt power supply pins for analog circuit and core  
logic.  
MODE - A low level on this pin causes pins 26, and 27 to be  
power management inputs PCI_STOP#, and CPU_STOP#  
respectly. A high level on this pin causes pins 26, and 27 to  
be clock output signals SDRAM7, and SDRAM6 respectively.  
It has an internal pull-up resistor.  
Vddq3 - Power supply pins for 3.3V IO pins.  
Vddq2 - Power supply pins for 2.5V/3.3V IO pins.  
PCICLK(0:5) - Low skew (<250pS) clock outputs for PCI  
frequencies.  
Vddq3  
These buffers voltage level is controlled by  
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.  
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571  
Rev.1.4  
8/10/98  
Page 2 of 15  
1234567...15

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