SG571D
I2C Frequency Clock Generator w/ EMI Reduction Spread Spectrum Technology
for Pentium Processor Based Designs.
Approved Product
PIN DESCRIPTION
Xin, Xout - These pins form an on-chip reference oscillator
when connected to terminals of an external parallel resonant
crystal (nominally 14.318 MHz). Xin may also serve as input
for an externally generated reference signal.
PCICLK_F - A PCI clock output that does not stop until in
power down mode. It is synchronous with other PCI clocks.
REF(0:2) - Buffered outputs of on-chip reference.
SEL - Standard frequency select input. It has internal pull-up.
IOAPIC0 - Buffered output of 14.3MHZ for multiprocessor
support. It is powered by Vddq2.
CPUCLK - Hose clock output primarily use to drive the
SDRAM.
PWR_DWN# - Power down pin. When this pin is asserted
low, the IC is in shutdown mode where all circuitry is turned
off including VCO, crystal buffer and PCICLK_F. It has an
internal pull-up. The I2C interface is disabled with the
PWR_DWN# pin is low.
CPUMCLK(0:1) - High drive host clock output primarily used
to drive Mobil Pentium processor modules.
SDRAM(0:5) - Synchronous DRAM DIMs clocks. They are
powered by Vddq3.
48/24MHz(0:1) - Programmable 48 MHZ or 24 MHZ clock
outputs.
SDRAM6/CPU_STOP#
-
If MODE=1, this pin is
a
SDATA - serial data of I2C 2-wire control interface. Has
internal pull-up resistor.
Synchronous DRAM DIMs clock output. If MODE=0, this pin
is a CPU_STOP# input signal, where a low level stops the
CPU however, the SDRAM clocks will stay active. It has an
internal pull-up.
SDCLK - serial clock of I2C 2-wire control interface. Has
internal pull-up resistor.
SDRAM7/PCI_STOP#
-
If MODE=1, this pin is
a
Vss - Ground pins for the chip.
Synchronous DRAM DIMs clock output. If MODE=0, this pin
is a PCI_STOP# input signal, where a low level stops the PCI
clocks. It has an internal pull-up.
Vdd - 3.3 Volt power supply pins for analog circuit and core
logic.
MODE - A low level on this pin causes pins 26, and 27 to be
power management inputs PCI_STOP#, and CPU_STOP#
respectly. A high level on this pin causes pins 26, and 27 to
be clock output signals SDRAM7, and SDRAM6 respectively.
It has an internal pull-up resistor.
Vddq3 - Power supply pins for 3.3V IO pins.
Vddq2 - Power supply pins for 2.5V/3.3V IO pins.
PCICLK(0:5) - Low skew (<250pS) clock outputs for PCI
frequencies.
Vddq3
These buffers voltage level is controlled by
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.4
8/10/98
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