IDTCSP2510CPG

更新时间： 2024-09-26 22:40:39

品牌	Logo	应用领域
艾迪悌 - IDT		时钟驱动器
页数	文件大小	规格书
9页	64K
描述
3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER

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IDTCSP2510CPG 数据手册

IDTCSP2510C

3.3VPHASE-LOCKLOOPCLOCKDRIVER

0ºCTO85ºCTEMPERATURERANGE

IDTCSP2510C

3.3V PHASE-LOCK LOOP

CLOCK DRIVER

ZERO DELAY BUFFER

FEATURES:

DESCRIPTION:

• Phase-Lock Loop Clock Distribution for Synchronous DRAM

Applications

TheCSP2510Cisahighperformance, low-skew, low-jitter, phase-lock

loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency

and phase, the feedback (FBOUT) output to the clock (CLK) input signal.

ItisspecificallydesignedforusewithsynchronousDRAMs.TheCSP2510C

operates at 3.3V.

• Distributes one clock input to one bank of ten outputs

• Output enable bank control

• External feedback (FBIN) pin is used to synchronize the

outputs to the clock input signal

• No external RC network required for PLL loop stability

• Operates at 3.3V VDD

• tpd Phase Error at 133MHz: < ±150ps

• Jitter (peak-to-peak) at 133MHz: < ±75ps @ 133MHz

• Spread Spectrum Compatible

One bank of ten outputs provide low-skew, low-jitter copies of CLK.

Output signal duty cycles are adjusted to 50 percent, independent of the

duty cycle at CLK. The outputs can be enabled or disabled via the control

Ginput.WhentheGinputishigh,theoutputsswitchinphaseandfrequency

withCLK;whentheGinputislow, theoutputsaredisabledtothelogic-low

state.

• Operating frequency 25MHz to 140MHz

• Available in 24-Pin TSSOP package

UnlikemanyproductscontainingPLLs,theCSP2510Cdoesnotrequire

external RC networks. The loop filter for the PLL is included on-chip,

minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CSP2510C requires a

stabilization time to achieve phase lock of the feedback signal to the

referencesignal.Thisstabilizationtimeisrequired,followingpowerupand

application of a fixed-frequency, fixed-phase signal at CLK, as well as

followinganychangestothePLLreferenceorfeedbacksignals. ThePLL

can be bypassed for the test purposes by strapping AVDD to ground.

The CSP2510C is specified for operation from 0°C to +85°C. This

deviceisalsoavailable(onspecialorder)inIndustrialtemperaturerange

(-40°C to +85°C). See ordering information for details.

APPLICATIONS:

• SDRAM Modules

• PC Motherboards

• Workstations

FUNCTIONALBLOCKDIAGRAM

CLK

PLL

FBIN

AV^DD

FBOUT

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

0ºC TO 85ºC TEMPERATURE RANGE

OCTOBER 2000

1999 Integrated Device Technology, Inc.

DSC-5180/2

12 3 4 5 6 7...9

中文翻译

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IDTCSP2510CPG 替代型号

型号	品牌	替代类型	描述	数据表
2510CGLF	IDT	功能相似	TSSOP-24, Tube
CDCVF2510APW	TI	功能相似	3.3-V Phase-Lock Loop Clock Driver with Power Down Mode 24-TSSOP 0 to 85

与IDTCSP2510CPG相关器件

型号	品牌	获取价格	描述	数据表
IDTCSP2510CPGG	IDT	获取价格	3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER
IDTCSP2510CPGG8	IDT	获取价格	PLL Based Clock Driver, 2510 Series, 10 True Output(s), 0 Inverted Output(s), PDSO24, TSSO
IDTCSP2510CPGGI	IDT	获取价格	3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER
IDTCSP2510CPGI	IDT	获取价格	3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER
IDTCSP2510CPGI8	IDT	获取价格	PLL Based Clock Driver, 2510 Series, 10 True Output(s), 0 Inverted Output(s), PDSO24, TSSO
IDTCSP2510D	IDT	获取价格	3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER
IDTCSP2510DP	IDT	获取价格	PLL Based Clock Driver, 2510 Series, 10 True Output(s), 0 Inverted Output(s), PDSO24, TSSO
IDTCSP2510DPG	IDT	获取价格	3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER
IDTCSP2510DPG8	IDT	获取价格	PLL Based Clock Driver, 2510 Series, 10 True Output(s), 0 Inverted Output(s), PDSO24, TSSO
IDTCSP2510DPGG	IDT	获取价格	PLL Based Clock Driver, 2510 Series, 10 True Output(s), 0 Inverted Output(s), PDSO24, TSSO

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