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IDTCSP5V993-5Q PDF预览

IDTCSP5V993-5Q

更新时间: 2024-09-27 20:07:07
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
8页 118K
描述
PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PDSO28, QSOP-28

IDTCSP5V993-5Q 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SSOP,针数:28
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.7输入调节:STANDARD
JESD-30 代码:R-PDSO-G28JESD-609代码:e0
长度:9.9 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
功能数量:1反相输出次数:
端子数量:28实输出次数:8
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.7 ns座面最大高度:1.75 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.9116 mm最小 fmax:70 MHz
Base Number Matches:1

IDTCSP5V993-5Q 数据手册

 浏览型号IDTCSP5V993-5Q的Datasheet PDF文件第2页浏览型号IDTCSP5V993-5Q的Datasheet PDF文件第3页浏览型号IDTCSP5V993-5Q的Datasheet PDF文件第4页浏览型号IDTCSP5V993-5Q的Datasheet PDF文件第5页浏览型号IDTCSP5V993-5Q的Datasheet PDF文件第6页浏览型号IDTCSP5V993-5Q的Datasheet PDF文件第7页 
3.3V PROGRAMMABLE  
SKEW PLL CLOCK DRIVER  
TURBOCLOCK™  
IDTCSP5V993  
FEATURES  
DESCRIPTION  
REF input is 5V tolerant  
The CSP5V993is a highfanout3.3VPLLbasedclockdriverintended  
forhighperformancecomputinganddata-communicationsapplications.A  
keyfeatureoftheprogrammableskewistheabilityofoutputstoleadorlag  
theREFinputsignal.TheCSP5V993hassixprogrammableskewoutputs  
andtwozeroskewoutputs.Skewiscontrolledby3-levelinputsignalsthat  
may be hard-wired to appropriate HIGH-MID-LOW levels.  
3pairs ofprogrammable skewoutputs  
Low skew: 200ps same pair, 250ps all outputs  
Selectable positive ornegative edge synchronization:  
ExcellentforDSPapplications  
Synchronous outputenable  
Outputfrequency: 6.25MHzto85MHz  
2x, 4x, 1/2, and 1/4 outputs  
3 skew grades:  
Whenthe GND/sOE pinis heldlow,allthe outputs are synchronously  
enabled.However,ifGND/sOEisheldhigh,alltheoutputsexcept3Q0and  
3Q1 are synchronously disabled.  
CSP5V993-2:tSKEW0<250ps  
CSP5V993-5:tSKEW0<500ps  
CSP5V993-7:tSKEW0<750ps  
3-level inputs for skew and PLL range control  
PLL bypass for DC testing  
Externalfeedback,internalloopfilter  
12mAbalanceddrive outputs  
Furthermore, when the VCCQ/PE is held high, all the outputs are  
synchronizedwiththe positive edge ofthe REFclockinput.WhenVCCQ/  
PEis heldlow,allthe outputs are synchronizedwiththe negative edge of  
REF. BothdeviceshaveLVTTLoutputswith12mAbalanceddriveoutputs.  
LowJitter: <200ps peak-to-peak  
Industrialtemperaturerange  
Available in28-pinQSOPPackage  
FUNCTIONALBLOCKDIAGRAM  
GND/sOE  
1Q0  
Skew  
Select  
1Q1  
3
3
3
3
1F1:0  
2F1:0  
3F1:0  
VCCQ/PE  
2Q0  
2Q1  
Skew  
Select  
3
REF  
PLL  
FB  
3Q0  
3Q1  
Skew  
Select  
3
3
FS  
4Q0  
4Q1  
COMMERCIAL/INDUSTRIAL TEMPERATURE RANGES  
FEBRUARY 2000  
1
c
2000 Integrated Device Technology, Inc.  
DSC-5787/-  

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