IDTCSPT857A

更新时间： 2024-11-14 22:40:19

品牌	Logo	应用领域
艾迪悌 - IDT		时钟驱动器动态存储器
页数	文件大小	规格书
12页	125K
描述
2.5V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER

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IDTCSPT857A 数据手册

IDTCSPT857/A

COMMERCIALANDINDUSTRIALTEMPERATURERANGES

2.5V PLLDIFFERENTIAL1:10SDRAMCLOCKDRIVER

2.5V PHASE LOCKED LOOP

DIFFERENTIAL 1:10 SDRAM

CLOCK DRIVER

IDTCSPT857/A

FEATURES:

DESCRIPTION:

• Optimized for clock distribution in DDR (Double Data Rate)

SDRAM applications

The CSPT857 is a PLL based clock driver that acts as a zero delay buffer

todistributeonedifferentialclockinputpair(CLK,CLK)to10differentialoutput

pairs(Y[0:9],Y[0:9])andonedifferentialpairoffeedbackclockoutput(FBOUT,

FBOUT). External feedback pins (FBIN, FBIN) for synchronization of the

• Operating frequency: 60MHz to 200MHz

• Standard speed: PC1600 (DDR200), PC2100 (DDR266)

• A speed: PC1600 (DDR200), PC2100 (DDR266), PC2700 (DDR333) outputs to the input reference is provided. A CMOS Enable/Disable pin is

• 1 to 10 differential clock distribution

• Very low skew (<100ps)

• Very low jitter (<75ps)

• 2.5V AVDD and 2.5V VDDQ

• CMOS control signal input

• Test mode enables buffers while disabling PLL

• Low current power-down mode

• Tolerant of Spread Spectrum input clock

• Available in 48-pin TSSOP and 56-pin VFBGA packages

available for low power disable. When the output frequency falls below

approximately20MHz,thedevicewillenterpowerdownmode. Inthismode,

thereceiversaredisabled,thePLListurnedoff,andtheoutputclockdrivers

aretristated,resultinginacurrentconsumptiondeviceoflessthan200µA.

TheCSPT857requiresnoexternalcomponentsandhasbeenoptimised

forverylowI/Ophaseerror,skew,andjitter,whilemaintainingfrequencyand

duty cycleovertheoperatingvoltageandtemperaturerange.TheCSPT857,

designedforuseinbothmoduleassembliesandsystemmotherboardbased

solutions,providesanoptimumhigh-performanceclocksource.

TheCSPT857isonlyavailableinIndustrialTemperatureRange(-40°Cto

+85°C),andCSPT857AisonlyavailableinCommercialTemperatureRange

(0°Cto+70°C). SeeOrderingInformationfordetails.

FUNCTIONALBLOCKDIAGRAM

37/E6

PWRDWN

TEST

MODE

LOGIC

3/A1

16/G2

2/A2

AV^DD

5/B2

6/B1

10/D1

9/D2

20/J2

19/J1

22/K1

23/K2

46/A6

13/F1

CLK

14/F2

47/A5

CLK

PLL

44/B5

36/F6

FBIN

35/F5

43/B6

FBIN

39/D6

40/D5

29/J5

30/J6

27/K6

26/K5

32/H6

FBOUT

33/H5

FBOUT

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

OCTOBER 2002

2002 Integrated Device Technology, Inc.

DSC-5172/8

12 3 4 5 6 7...12

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与IDTCSPT857A相关器件

型号	品牌	获取价格	描述	数据表
IDTCSPT857ABV	IDT	获取价格	2.5V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
IDTCSPT857ABV8	IDT	获取价格	PLL Based Clock Driver, CSPT857 Series, 10 True Output(s), 0 Inverted Output(s), VFBGA-56
IDTCSPT857ABVI	IDT	获取价格	2.5V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
IDTCSPT857APA	IDT	获取价格	2.5V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
IDTCSPT857APA8	IDT	获取价格	PLL Based Clock Driver, CSPT857 Series, 10 True Output(s), 0 Inverted Output(s), PDSO48, T
IDTCSPT857APAI	IDT	获取价格	2.5V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
IDTCSPT857BV	IDT	获取价格	2.5V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
IDTCSPT857BV8	IDT	获取价格	PLL Based Clock Driver, CSPT857 Series, 10 True Output(s), 0 Inverted Output(s), VFBGA-56
IDTCSPT857BVI	IDT	获取价格	2.5V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
IDTCSPT857BVI8	IDT	获取价格	PLL Based Clock Driver, CSPT857 Series, 10 True Output(s), 0 Inverted Output(s), VFBGA-56

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