Datasheet > IDTCSPF2510CPGG

IDTCSPF2510CPGG

更新时间： 2024-09-27 04:15:31

品牌	Logo	应用领域
艾迪悌 - IDT		时钟驱动器
页数	文件大小	规格书
8页	66K
描述
3.3V PHASE-LOCK LOOP CLOCK DRIVER

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IDTCSPF2510CPGG 数据手册

IDTCSPF2510C

0ºCTO85ºCTEMPERATURERANGE

3.3V PHASE-LOCKLOOPCLOCKDRIVER

IDTCSPF2510C

3.3V PHASE-LOCK LOOP

CLOCK DRIVER

frequencyandphase,thefeedback(FBOUT)outputtotheclock(CLK)input

signal. It is specifically designed for use with synchronous DRAMs. The

CSPF2510C operates at 3.3V and provides integrated series-damping

resistors that make it ideal for driving point-to-point loads, single or dual.

Onebankoftenoutputsprovidelow-skew,low-jittercopiesofCLK.Output

signaldutycyclesareadjustedto50percent, independentofthedutycycle

atCLK.TheoutputscanbeenabledordisabledviathecontrolGinput.When

theGinputishigh,theoutputsswitchinphaseandfrequencywithCLK;when

the G input is low, the outputs are disabled to the logic-low state.

UnlikemanyproductscontainingPLLs,theCSPF2510Cdoesnotrequire

external RC networks. The loop filter for the PLL is included on-chip,

minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CSPF2510C requires a

stabilizationtimetoachievephaselockofthefeedbacksignaltothereference

signal.Thisstabilizationtimeisrequired,followingpowerupandapplication

of a fixed-frequency, fixed-phase signal at CLK, as well as following any

changes to the PLL reference or feedback signals. The PLL can be

bypassed for the test purposes by strapping AVDD to ground.

FEATURES:

• Phase-Lock Loop Clock Distribution for Synchronous DRAM

Applications

• Distributes one clock input to one bank of ten outputs

• Output enable bank control

• External feedback (FBIN) pin is used to synchronize the output

to the clock input signal

• On-chip series damping resistors with each driver

• No external RC network required for PLL loop stability

• Operates at 3.3V VDD

• tpd Phase Error at 133MHz: < ±150ps

• Jitter (cycle-cycle)(peak-to-peak) at 66MHz to 133MHz: | 70 | ps

• Spread Spectrum Compatible

• Operating frequency 25MHz to 140MHz

• Fully conforms to PC133 specifications

• Available in 24-Pin TSSOP package

DESCRIPTION:

TheCSPF2510Cischaracterizedforoperationfrom0°Cto+85°C. This

device is also available (on special order) in Industrial (-40°C to +85°C)

temperatures. See Ordering Information for more details.

The IDTCSPF2510C is a high performance, low-skew, low-jitter,

phase-lockloop(PLL)clockdriver. ItusesaPLLtopreciselyalign, inboth

FUNCTIONALBLOCKDIAGRAM

CLK

PLL

FBIN

AV^DD

FBOUT

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

0ºC TO 85ºC TEMPERATURE RANGE

AUGUST 2002

2002 Integrated Device Technology, Inc.

DSC-5409/6

12 3 4 5 6 7 8

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与IDTCSPF2510CPGG相关器件

型号	品牌	获取价格	描述	数据表
IDTCSPF2510CPGGI	IDT	获取价格	3.3V PHASE-LOCK LOOP CLOCK DRIVER
IDTCSPF2510CPGI	IDT	获取价格	3.3V PHASE-LOCK LOOP CLOCK DRIVER
IDTCSPF2510CPGI8	IDT	获取价格	PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), PDSO24, TSSOP-24
IDTCSPT855PG8	IDT	获取价格	PLL Based Clock Driver, 855 Series, 4 True Output(s), 0 Inverted Output(s), PDSO28, TSSOP-
IDTCSPT855PGG	IDT	获取价格	PLL Based Clock Driver, 855 Series, 4 True Output(s), 0 Inverted Output(s), PDSO28, GREEN,
IDTCSPT855PGG8	IDT	获取价格	PLL Based Clock Driver, 855 Series, 4 True Output(s), 0 Inverted Output(s), PDSO28, GREEN,
IDTCSPT855PGGI	IDT	获取价格	PLL Based Clock Driver, 855 Series, 4 True Output(s), 0 Inverted Output(s), PDSO28, GREEN,
IDTCSPT857	IDT	获取价格	2.5V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
IDTCSPT857A	IDT	获取价格	2.5V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
IDTCSPT857ABV	IDT	获取价格	2.5V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER

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