Datasheet > IDTCSPF2510CPG

IDTCSPF2510CPG

更新时间： 2024-09-27 04:15:31

品牌	Logo	应用领域
艾迪悌 - IDT		时钟驱动器
页数	文件大小	规格书
8页	66K
描述
3.3V PHASE-LOCK LOOP CLOCK DRIVER

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技术参数
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IDTCSPF2510CPG 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	TSSOP	包装说明：	TSSOP, TSSOP24,.25
针数：	24	Reach Compliance Code：	not_compliant
HTS代码：	8542.39.00.01	风险等级：	5.31
输入调节：	STANDARD	JESD-30 代码：	R-PDSO-G24
JESD-609代码：	e0	长度：	7.8 mm
逻辑集成电路类型：	PLL BASED CLOCK DRIVER	最大I（ol）：	0.012 A
湿度敏感等级：	1	功能数量：	1
反相输出次数：		端子数量：	24
实输出次数：	10	最高工作温度：	85 °C
最低工作温度：		输出特性：	SERIES-RESISTOR
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装等效代码：	TSSOP24,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	电源：	3.3 V
认证状态：	Not Qualified	Same Edge Skew-Max（tskwd）：	0.15 ns
座面最大高度：	1.2 mm	子类别：	Clock Drivers
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
温度等级：	OTHER	端子面层：	Tin/Lead (Sn85Pb15)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	宽度：	4.4 mm
最小 fmax：	140 MHz

IDTCSPF2510CPG 数据手册

IDTCSPF2510C

0ºCTO85ºCTEMPERATURERANGE

3.3V PHASE-LOCKLOOPCLOCKDRIVER

IDTCSPF2510C

3.3V PHASE-LOCK LOOP

CLOCK DRIVER

frequencyandphase,thefeedback(FBOUT)outputtotheclock(CLK)input

signal. It is specifically designed for use with synchronous DRAMs. The

CSPF2510C operates at 3.3V and provides integrated series-damping

resistors that make it ideal for driving point-to-point loads, single or dual.

Onebankoftenoutputsprovidelow-skew,low-jittercopiesofCLK.Output

signaldutycyclesareadjustedto50percent, independentofthedutycycle

atCLK.TheoutputscanbeenabledordisabledviathecontrolGinput.When

theGinputishigh,theoutputsswitchinphaseandfrequencywithCLK;when

the G input is low, the outputs are disabled to the logic-low state.

UnlikemanyproductscontainingPLLs,theCSPF2510Cdoesnotrequire

external RC networks. The loop filter for the PLL is included on-chip,

minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CSPF2510C requires a

stabilizationtimetoachievephaselockofthefeedbacksignaltothereference

signal.Thisstabilizationtimeisrequired,followingpowerupandapplication

of a fixed-frequency, fixed-phase signal at CLK, as well as following any

changes to the PLL reference or feedback signals. The PLL can be

bypassed for the test purposes by strapping AVDD to ground.

FEATURES:

• Phase-Lock Loop Clock Distribution for Synchronous DRAM

Applications

• Distributes one clock input to one bank of ten outputs

• Output enable bank control

• External feedback (FBIN) pin is used to synchronize the output

to the clock input signal

• On-chip series damping resistors with each driver

• No external RC network required for PLL loop stability

• Operates at 3.3V VDD

• tpd Phase Error at 133MHz: < ±150ps

• Jitter (cycle-cycle)(peak-to-peak) at 66MHz to 133MHz: | 70 | ps

• Spread Spectrum Compatible

• Operating frequency 25MHz to 140MHz

• Fully conforms to PC133 specifications

• Available in 24-Pin TSSOP package

DESCRIPTION:

TheCSPF2510Cischaracterizedforoperationfrom0°Cto+85°C. This

device is also available (on special order) in Industrial (-40°C to +85°C)

temperatures. See Ordering Information for more details.

The IDTCSPF2510C is a high performance, low-skew, low-jitter,

phase-lockloop(PLL)clockdriver. ItusesaPLLtopreciselyalign, inboth

FUNCTIONALBLOCKDIAGRAM

CLK

PLL

FBIN

AV^DD

FBOUT

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

0ºC TO 85ºC TEMPERATURE RANGE

AUGUST 2002

2002 Integrated Device Technology, Inc.

DSC-5409/6

12 3 4 5 6 7 8

中文翻译

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与IDTCSPF2510CPG相关器件

型号	品牌	获取价格	描述	数据表
IDTCSPF2510CPG8	IDT	获取价格	PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), PDSO24, TSSOP-24
IDTCSPF2510CPGG	IDT	获取价格	3.3V PHASE-LOCK LOOP CLOCK DRIVER
IDTCSPF2510CPGGI	IDT	获取价格	3.3V PHASE-LOCK LOOP CLOCK DRIVER
IDTCSPF2510CPGI	IDT	获取价格	3.3V PHASE-LOCK LOOP CLOCK DRIVER
IDTCSPF2510CPGI8	IDT	获取价格	PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), PDSO24, TSSOP-24
IDTCSPT855PG8	IDT	获取价格	PLL Based Clock Driver, 855 Series, 4 True Output(s), 0 Inverted Output(s), PDSO28, TSSOP-
IDTCSPT855PGG	IDT	获取价格	PLL Based Clock Driver, 855 Series, 4 True Output(s), 0 Inverted Output(s), PDSO28, GREEN,
IDTCSPT855PGG8	IDT	获取价格	PLL Based Clock Driver, 855 Series, 4 True Output(s), 0 Inverted Output(s), PDSO28, GREEN,
IDTCSPT855PGGI	IDT	获取价格	PLL Based Clock Driver, 855 Series, 4 True Output(s), 0 Inverted Output(s), PDSO28, GREEN,
IDTCSPT857	IDT	获取价格	2.5V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER

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