Datasheet > IDTCSP5V9910-2SO

IDTCSP5V9910-2SO

更新时间： 2024-09-28 06:18:27

品牌	Logo	应用领域
艾迪悌 - IDT		光电二极管
页数	文件大小	规格书
6页	95K
描述
PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PDSO24, 0.300 INCH, SOIC-24

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IDTCSP5V9910-2SO 数据手册

IDTCSP5V9910

3.3VLOWSKEWPLLCLOCKDRIVERTURBOCLOCKJR.

COMMERCIALANDINDUSTRIALTEMPERATURERANGES

3.3V LOW SKEW

IDTCSP5V9910

PLL CLOCK DRIVER

TURBOCLOCK™ JR.

FEATURES:

DESCRIPTION

•

EightzerodelayLVTTLoutputs

<250ps ofoutputtooutputskew

Selectable positive ornegative edge synchronization

Synchronous outputenable

Outputfrequency:25MHzto70MHz

3 skew grades:

CSP5V9910-2:t_SKEW0<250ps

CSP5V9910-5:t_SKEW0<500ps

CSP5V9910-7:t_SKEW0<750ps

3-level input for PLL range control

PLL bypass for DC testing

Externalfeedback,internalloopfilter

12mAbalanceddrive outputs

LowJitter:<200ps peak-to-peak

Available inSOICPackage

The CSP5V9910 is a high fanout phase locked-loop clock driver

intendedforhighperformancecomputinganddata-communicationsappli-

cations. Ithas eightzerodelayLVTTLoutputs.

Whenthe GND/sOEpinis heldlow,allthe outputs are synchronously

enabled.However,ifGND/sOEis heldhigh,alltheoutputs exceptQ2 and

Q3 are synchronouslydisabled.

Furthermore, when the VCCQ/PE is held high, all the outputs are

synchronizedwiththe positive edge ofthe REFclockinput.WhenVCCQ/

PEis heldlow,allthe outputs are synchronizedwiththe negative edge of

REF.

•

TheFBsignaliscomparedwiththeinputREFsignalatthephasedetector

inordertodrive the VCO.Phase differences cause the VCOofthe PLLto

adjust upwards or downwards accordingly.

Aninternalloopfiltermoderates the response ofthe VCOtothe phase

detector. The loop filter transfer function has been chosen to provide

minimal jitter (or frequency variation) while still providing accurate re-

sponses toinputfrequencychanges.

FUNCTIONALBLOCKDIAGRAM

VCCQ/PE

GND/sOE

PLL

REF

COMMERCIAL/INDUSTRIAL TEMPERATURE RANGES

FEBRUARY 2000

2000 Integrated Device Technology, Inc.

DSC-5808/-

12 3 4 5 6

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