Datasheet > IDTCSP5991-7JR

IDTCSP5991-7JR

更新时间： 2024-09-28 10:08:55

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
8页	123K
描述
PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQCC32, PLASTIC, LCC-32

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IDTCSP5991-7JR 数据手册

IDTCSP5991

COMMERCIALANDINDUSTRIALTEMPERATURERANGES

PROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCK

PROGRAMMABLE SKEW

PLL CLOCK DRIVER

TURBOCLOCK™

IDTCSP5991

FEATURES:

DESCRIPTION:

•

4pairsofprogrammableskewoutputs

Lowskew:200ps samepair,250ps alloutputs

Selectablepositiveornegativeedgesynchronization:

ExcellentforDSPapplications

Synchronousoutputenable

Outputfrequency:6.25MHzto100MHz

2x, 4x, 1/2, and 1/4 outputs

5VwithTTLoutputs

3 skew grades:

CSP5991-2:tSKEW0<250ps

CSP5991-5:tSKEW0<500ps

CSP5991-7:tSKEW0<750ps

3-level inputs for skew and PLL range control

PLLbypass forDCtesting

Externalfeedback,internalloopfilter

46mAIOLhighdriveoutputs

LowJitter:<200pspeak-to-peak

Outputsdrive50Ωterminatedlines

PincompatiblewithCypressCY7B991

Available inPLCCPackage

The CSP5991 is a high fanout PLL based clock driver intended for

high performance computing and data-communications applications. A

key feature of the programmable skew is the ability of outputs to lead or

lag the REF input signal. The CSP5991 has eight programmable skew

outputs in four banks of 2. Skew is controlled by 3-level input signals

that may be hard-wired to appropriate HIGH-MID-LOW levels.

•

The CSP5991 maintains Cypress CY7B991 compatibility while pro-

viding two additional features: Synchronous Output Enable (GND/sOE),

and Positive/Negative Edge Synchronization (V^CCQ/PE). When the GND/

sOE pin is held low, all the outputs are synchronously enabled (CY7B991

compatibility). However, if GND/sOE is held high, all the outputs except

3Q0 and 3Q1 are synchronously disabled.

•

Furthermore, when the VCCQ/PE is held high, all the outputs are

synchronized with the positive edge of the REF clock input (CY7B991

compatibility). When VCCQ/PE is held low, all the outputs are synchro-

nized with the negative edge of REF.

FUNCTIONALBLOCKDIAGRAM

GND/sOE

1Q0

Skew

Select

1Q1

1F1:0

VCCQ/PE

2Q0

2Q1

Skew

Select

REF

PLL

2F1:0

3Q0

3Q1

Skew

Select

3F1:0

4Q0

4Q1

Skew

Select

4F1:0

COMMERCIAL/INDUSTRIAL TEMPERATURE RANGES

FEBRUARY 2000

2000 Integrated Device Technology, Inc.

DSC-5809/-

12 3 4 5 6 7 8

中文翻译

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与IDTCSP5991-7JR相关器件

型号	品牌	获取价格	描述	数据表
IDTCSP5991-7JRI	IDT	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQCC32, PLASTIC, LCC-32
IDTCSP59920-7SO	IDT	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PDSO24, 0.300 INCH, SOIC-2
IDTCSP59920-7SOI	IDT	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PDSO24, 0.300 INCH, SOIC-2
IDTCSP5V9910-2SO	IDT	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PDSO24, 0.300 INCH, SOIC-2
IDTCSP5V9910-5SO	IDT	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PDSO24, 0.300 INCH, SOIC-2
IDTCSP5V9910-7SOI	IDT	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PDSO24, 0.300 INCH, SOIC-2
IDTCSP5V993-5Q	IDT	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PDSO28, QSOP-28
IDTCSP5V993-7QI	IDT	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PDSO28, QSOP-28
IDTCSPF2510C	IDT	获取价格	3.3V PHASE-LOCK LOOP CLOCK DRIVER
IDTCSPF2510CPG	IDT	获取价格	3.3V PHASE-LOCK LOOP CLOCK DRIVER

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