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IDT74LVCH16543APF8

更新时间： 2024-09-16 20:51:27
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管输出元件逻辑集成电路电视
页数 文件大小 规格书
6页 81K
描述
Registered Bus Transceiver, LVC/LCX/Z Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, TVSOP-56

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IDT74LVCH16543APF8 技术参数

生命周期：Obsolete零件包装代码：SSOP
包装说明：TSSOP,针数：56
Reach Compliance Code：unknown风险等级：5.64
其他特性：WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION系列：LVC/LCX/Z
JESD-30 代码：R-PDSO-G56JESD-609代码：e0
长度：11.3 mm逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
位数：8功能数量：2
端口数量：2端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟（tpd）：7.4 ns认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：TIN LEAD
端子形式：GULL WING端子节距：0.4 mm
端子位置：DUAL宽度：4.4 mm
Base Number Matches：1

IDT74LVCH16543APF8 数据手册

 浏览型号IDT74LVCH16543APF8的Datasheet PDF文件第2页浏览型号IDT74LVCH16543APF8的Datasheet PDF文件第3页浏览型号IDT74LVCH16543APF8的Datasheet PDF文件第4页浏览型号IDT74LVCH16543APF8的Datasheet PDF文件第5页浏览型号IDT74LVCH16543APF8的Datasheet PDF文件第6页 
3.3V CMOS 16-BIT  
REGISTERED TRANSCEIVER  
WITH 3-STATE OUTPUTS,  
IDT74LVCH16543A  
5 VOLT TOLERANT I/O, BUS-HOLD  
FEATURES:  
DESCRIPTION  
• Typical tSK(o) (Output Skew) < 250ps  
The LVCH16543A 16-bit registered transceiver is built using advanced  
dualmetalCMOStechnology. TheLVCH16543Acanbeusedastwo8-bit  
transceivers or one 16-bit transceiver. Separate latch-enable (LEAB or  
LEBA) and output-enable (OEAB or OEBA) inputs are provided for each  
register to permit independent control in either direction of data flow. The  
A-to-B enable (CEAB) input must be low in order to enter data from the A  
portortooutput data fromtheBport. LEABcontrolsthelatch function. When  
LEAB is low, the A to B latches are transparent. A subsequent low-to-high  
transitionofLEABputstheAlatchesinthestoragemode. OEABperforms  
outputenablefunctionontheBport. DataflowfromtheBporttotheAport  
issimilarbutrequiresusingCEBA,LEBA, andOEBAinputs. Flow-through  
organization of signal pins simplifies layout. All inputs are designed with  
hysteresis for improved noise margin.  
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using  
machine model (C = 200pF, R = 0)  
• VCC = 3.3V ± 0.3V, Normal Range  
• VCC = 2.7V to 3.6V, Extended Range  
• CMOS power levels (0.4µ W typ. static)  
• All inputs, outputs, and I/O are 5V tolerant  
• Supports hot insertion  
• Available in SSOP, TSSOP, and TVSOP packages  
DRIVE FEATURES:  
• High Output Drivers: ±24mA  
• Reduced system switching noise  
Allpinsofthis16-bitregisteredtransceivercanbedrivenfromeither3.3V  
or 5V devices. This feature allows the use of this device as a translator in  
a mixed 3.3V/5V supply system.  
TheLVCH16543Ahasbeendesignedwitha ±24mA output driver. This  
driver is capable of driving a moderate to heavy load while maintaining  
speedperformance.  
APPLICATIONS:  
• 5V and 3.3V mixed voltage systems  
• Data communication and telecommunication systems  
The LVCH16543A has “bus-hold” which retains the inputs’ last state  
whenevertheinputgoestoahighimpedance. Thispreventsfloatinginputs  
and eliminates the need for pull-up/down resistors.  
FUNCTIONALBLOCKDIAGRAM  
29  
56  
2OEBA  
1OEBA  
31  
54  
2CEBA  
1CEBA  
30  
55  
2LEBA  
1LEBA  
28  
1
2OEAB  
1OEAB  
26  
3
2CEAB  
1CEAB  
2
27  
2LEAB  
1LEAB  
C1  
C1  
15  
2A1  
5
1A1  
42  
52  
2B1  
1B1  
1D  
1D  
C1  
1D  
C1  
1D  
TO SEVEN OTHER CHANNELS  
TO SEVEN OTHER CHANNELS  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
JULY 1999  
1
© 1999 Integrated Device Technology, Inc.  
DSC-4612/1  
123456

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IDT74LVCH16543APV8 IDT

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IDT74LVCH16601APA ETC

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IDT74LVCH16601APF ETC

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IDT74LVCH16601APF8 IDT

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 		18-Bit Bus Transceiver
IDT74LVCH16601APV8 IDT

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IDT74LVCH16601APVG8 IDT

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IDT74LVCH16646APA IDT

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 		3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER WITH 3-STATE OUTPUTS 5 VOLT TOLERANT I/O AND BUS

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