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IDT74FCT163601A

更新时间: 2024-09-14 23:11:43
品牌 Logo 应用领域
艾迪悌 - IDT 总线收发器输出元件
页数 文件大小 规格书
7页 108K
描述
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

IDT74FCT163601A 数据手册

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IDT74FCT163601/A  
ADVANCE INFORMATION  
3.3V CMOS  
18-BIT UNIVERSAL BUS  
TRANSCEIVER  
Integrated Device Technology, Inc.  
WITH 3-STATE OUTPUTS  
FEATURES:  
• 0.5 MICRON CMOS Technology  
universal bus transceivers combine D-type latches and D-  
type flip-flops to allow data flow in transparent, latched and  
clocked modes.  
Typical tSK(o) (Output Skew) < 250ps  
• ESD > 2000V per MIL-STD-883, Method 3015;  
> 200V using machine model (C = 200pF, R = 0)  
• Packages include 25 mil pitch SSOP, 19.6 mil pitch  
TSSOP and 15.7 mil pitch TVSOP  
• Extended commercial range of -40°C to +85°C  
• VCC = 3.3V ±0.3V, Normal Range or  
VCC = 2.7 to 3.6V, Extended Range  
• CMOS power levels (0.4µW typ. static)  
• Rail-to-Rail output swing for increased noise margin  
• Low Ground Bounce (0.3V typ.)  
• Inputs (except I/O) can be driven by 3.3V or 5V  
components  
Data flow in each direction is controlled by output-enable  
(OEABandOEBA), latch-enable(LEABandLEBA), andclock  
(CLKAB and CLKBA) inputs. The clock can be controlled by  
theclock-enable(CLKENAB andCLKENBA)inputs. ForA-to-  
Bdataflow,thedeviceoperatesinthetransparentmodewhen  
LEAB is high. When LEAB is low, the A data is latched if  
CLKAB is held at a high or low logic level. If LEAB is low, the  
A-bus data is stored in the latch/flip-flop on the low-to-high  
transition of CLKAB. Output enable OEAB is active low.  
When OEAB is low, the outputs are active. When OEAB is  
high, the outputs are in the high-impedance state.  
DataflowforBtoAissimilartothatofAtoBbutusesOEBA,  
LEBA, CLKBA and CLKENBA.  
TheFCT163601hasseriescurrentlimitingresistors. These  
offer low ground bounce, minimal undershoot, and controlled  
output fall times-reducing the need for external series termi-  
nating resistors.  
DESCRIPTION:  
The FCT163601/A 18-bit registered transceiver is built  
using advanced dual metal CMOS technology. These 18-bit  
FUNCTIONAL BLOCK DIAGRAM  
1
OEAB  
56  
CLKENAB  
55  
CLKAB  
2
LEAB  
28  
LEBA  
30  
CLKBA  
29  
CLKENBA  
27  
OEBA  
CE  
1D  
C1  
3
54  
A1  
B1  
CLK  
CE  
1D  
C1  
CLK  
3251 drw 01  
TO 17 OTHER CHANNELS  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
COMMERCIAL TEMPERATURE RANGE  
AUGUST 1996  
1996 Integrated Device Technology, Inc.  
5.9  
DSC-3251/1  
1

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