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IDT74FCT163646APVG PDF预览

IDT74FCT163646APVG

更新时间: 2024-11-06 13:02:23
品牌 Logo 应用领域
艾迪悌 - IDT 总线收发器
页数 文件大小 规格书
9页 158K
描述
Registered Bus Transceiver, FCT Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, SSOP-56

IDT74FCT163646APVG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP,针数:56
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.65其他特性:DIRECTION CONTROL; SELECT INPUT FOR MULTIPLEXED TRANSMISSION OF REGISTERED OR REAL TIME DATA
系列:FCTJESD-30 代码:R-PDSO-G56
JESD-609代码:e3长度:18.415 mm
负载电容(CL):50 pF逻辑集成电路类型:REGISTERED BUS TRANSCEIVER
湿度敏感等级:1位数:8
功能数量:2端口数量:2
端子数量:56最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):260
传播延迟(tpd):6.3 ns认证状态:Not Qualified
座面最大高度:2.794 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:7.5 mmBase Number Matches:1

IDT74FCT163646APVG 数据手册

 浏览型号IDT74FCT163646APVG的Datasheet PDF文件第2页浏览型号IDT74FCT163646APVG的Datasheet PDF文件第3页浏览型号IDT74FCT163646APVG的Datasheet PDF文件第4页浏览型号IDT74FCT163646APVG的Datasheet PDF文件第5页浏览型号IDT74FCT163646APVG的Datasheet PDF文件第6页浏览型号IDT74FCT163646APVG的Datasheet PDF文件第7页 
IDT74FCT163646/A/C  
3.3V CMOS  
16-BIT BUS TRANSCEIVER/  
REGISTERS  
Integrated Device Technology, Inc.  
FEATURES:  
DESCRIPTION:  
The FCT163646/A/C 16-bit registered transceivers are  
built using advanced dual metal CMOS technology. These  
high-speed, low-power devices are organized as two inde-  
pendant 8-bit bus transceivers with 3-state D-type registers.  
The control circuitry is organized for multiplexed transmission  
of data between A bus and B bus either directly or from the  
internal storage registers. Each 8-bit transceiver/register  
features direction control (xDIR), over-riding Output Enable  
control (xOE) and Select lines (xSAB and xSBA) to select  
either real-time data or stored data. Separate clock inputs are  
provided for A and B port registers. Data on the A or B data  
bus, or both, can be stored in the internal registers by the  
LOW-to-HIGH transitions at the appropriate clock pins. Flow-  
through organization of signal pins simplifies layout. All inputs  
are designed with hysteresis for improved noise margin.  
The FCT163646/A/C have series current limiting resistors.  
This offers low ground bounce, minimal undershoot, and  
controlled output fall times-reducing the need for external  
series terminating resistors.  
• 0.5 MICRON CMOS Technology  
Typical tSK(o) (Output Skew) < 250ps  
• ESD > 2000V per MIL-STD-883, Method 3015;  
> 200V using machine model (C = 200pF, R = 0)  
• Packages include 25 mil pitch SSOP, 19.6 mil pitch  
TSSOP and 15.7 mil pitch TVSOP  
• Extended commercial range of -40°C to +85°C  
• VCC = 3.3V ±0.3V, Normal Range or  
VCC = 2.7 to 3.6V, Extended Range  
• CMOS power levels (0.4µW typ. static)  
• Rail-to-Rail output swing for increased noise margin  
• Low Ground Bounce (0.3V typ.)  
• Inputs (except I/O) can be driven by 3.3V or 5V  
components  
FUNCTIONAL BLOCK DIAGRAM  
2OE  
1OE  
2DIR  
1DIR  
1CLKBA  
1SBA  
2CLKBA  
2SBA  
1CLKAB  
2CLKAB  
1SAB  
2SAB  
B REG  
D
B REG  
D
C
C
1B1  
A REG  
2B1  
A REG  
1A1  
2A1  
D
D
C
C
TO 7 OTHER CHANNELS  
TO 7 OTHER CHANNELS  
2778drw02  
2778drw01  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
COMMERCIAL TEMPERATURE RANGES  
AUGUST 1996  
1996 Integrated Device Technology, Inc.  
DSC-2778/6  
8.8  
1

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