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IDT74FCT163543APV8 PDF预览

IDT74FCT163543APV8

更新时间: 2024-09-15 21:18:31
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
7页 83K
描述
Registered Bus Transceiver, FCT Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, SSOP-56

IDT74FCT163543APV8 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SSOP包装说明:SSOP-56
针数:56Reach Compliance Code:not_compliant
风险等级:5.49其他特性:WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
控制类型:INDEPENDENT CONTROL计数方向:BIDIRECTIONAL
系列:FCTJESD-30 代码:R-PDSO-G56
JESD-609代码:e0长度:18.415 mm
负载电容(CL):50 pF逻辑集成电路类型:REGISTERED BUS TRANSCEIVER
最大I(ol):0.024 A湿度敏感等级:1
位数:8功能数量:2
端口数量:2端子数量:56
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP56,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:3/3.3 V
Prop。Delay @ Nom-Sup:6.5 ns传播延迟(tpd):8 ns
认证状态:Not Qualified座面最大高度:2.794 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
翻译:N/A宽度:7.5 mm
Base Number Matches:1

IDT74FCT163543APV8 数据手册

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3.3V CMOS 16-BIT  
LATCHED TRANSCEIVER  
IDT74FCT163543A/C  
DESCRIPTION:  
FEATURES:  
The FCT163543 16-bit latched transceivers are built using advanced  
dual metal CMOS technology. These high-speed, low-power devices are  
organized as two independent 8-bit D-type latched transceivers with  
separateinputandoutputcontroltopermitindependentcontrolofdataflow  
in either direction. For example, the A-to-B Enable (xCEAB) must be low  
inordertoenterdatafromtheAportortooutputdatafromtheBport. xLEAB  
controlsthelatchfunction. WhenxLEABislow,thelatchesaretransparent.  
A subsequent low-to-high transition of xLEAB signal puts the A latches in  
the storage mode. xOEAB performs output enable function on the B port.  
Data flow from the B port to the A port is similar but requires using xCEBA,  
xLEBA, and xOEBA inputs. Flow-through organization of signal pins  
simplifieslayout.Allinputsaredesignedwithhysteresisforimprovednoise  
margin.  
• 0.5 MICRON CMOS Technology  
• Typical tSK(o) (Output Skew) < 250ps  
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using  
machine model (C = 200pF, R = 0)  
• VCC = 3.3V ± 0.3V, Normal Range, or VCC = 2.7V to 3.6V, Extended  
Range  
• CMOS power levels (0.4µ W typ. static)  
• Rail-to-rail output swing for increased noise margin  
• Low Ground Bounce (0.3V typ.)  
• Inputs (except I/O) can be driven by 3.3V or 5V components  
• Available in SSOP and TSSOP packages  
TheFCT163543haveseriescurrentlimitingresistors. Theseofferlow  
ground bounce, minimal undershoot, and controlled output fall times–  
reducing the need for external series terminating resistors.  
FUNCTIONALBLOCKDIAGRAM  
29  
56  
2OEBA  
1OEBA  
31  
54  
2CEBA  
1CEBA  
55  
30  
28  
2LEBA  
2OEAB  
1LEBA  
1
1OEAB  
26  
27  
3
2CEAB  
2LEAB  
1CEAB  
2
1LEAB  
C
D
C
5
2A1  
1A1  
52  
42  
2B1  
1B1  
D
C
D
C
D
TO SEVEN OTHER CHANNELS  
TO SEVEN OTHER CHANNELS  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
MAY 2002  
1
©
2002 Integrated Device Technology, Inc.  
DSC-3250/5  

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