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IDT74FCT163543PVT/R PDF预览

IDT74FCT163543PVT/R

更新时间： 2024-09-15 13:08:47
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
7页 107K
描述
Registered Bus Transceiver, FCT Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, 0.025 INCH PITCH, SSOP-56

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IDT74FCT163543PVT/R 技术参数

生命周期：Obsolete零件包装代码：SSOP
包装说明：SSOP,针数：56
Reach Compliance Code：unknown风险等级：5.49
其他特性：WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION系列：FCT
JESD-30 代码：R-PDSO-G56JESD-609代码：e0
长度：18.415 mm负载电容（CL）：50 pF
逻辑集成电路类型：REGISTERED BUS TRANSCEIVER位数：8
功能数量：2端口数量：2
端子数量：56最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH传播延迟（tpd）：12.5 ns
认证状态：Not Qualified座面最大高度：2.794 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：TIN LEAD端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
宽度：7.5 mmBase Number Matches：1

IDT74FCT163543PVT/R 数据手册

 浏览型号IDT74FCT163543PVT/R的Datasheet PDF文件第2页浏览型号IDT74FCT163543PVT/R的Datasheet PDF文件第3页浏览型号IDT74FCT163543PVT/R的Datasheet PDF文件第4页浏览型号IDT74FCT163543PVT/R的Datasheet PDF文件第5页浏览型号IDT74FCT163543PVT/R的Datasheet PDF文件第6页浏览型号IDT74FCT163543PVT/R的Datasheet PDF文件第7页 
IDT74FCT163543/A/C  
ADVANCE INFORMATION  
3.3V CMOS  
16-BIT LATCHED  
TRANSCEIVER  
Integrated Device Technology, Inc.  
FEATURES:  
DESCRIPTION:  
• 0.5 MICRON CMOS Technology  
The FCT163543/A/C 16-bit latched transceivers are built  
• Typical tSK(o) (Output Skew) < 250ps  
• ESD > 2000V per MIL-STD-883, Method 3015;  
> 200V using machine model (C = 200pF, R = 0)  
• Packages include 25 mil pitch SSOP, 19.6 mil pitch  
TSSOP and 15.7 mil pitch TVSOP  
• Extended commercial range of -40°C to +85°C  
• VCC = 3.3V ±0.3V, Normal Range or  
VCC = 2.7 to 3.6V, Extended Range  
• CMOS power levels (0.4µW typ. static)  
• Rail-to-Rail output swing for increased noise margin  
• Low Ground Bounce (0.3V typ.)  
• Inputs (except I/O) can be driven by 3.3V or 5V  
components  
using advanced dual metal CMOS technology. These high-  
speed,low-powerdevicesareorganizedastwoindependent8-  
bit D-type latched transceivers with separate input and output  
control to permit independent control of data flow in either  
direction. For example, the A-to-B Enable (xCEAB) must be  
LOWinordertoenterdatafromtheAportortooutputdatafrom  
the B port. xLEAB controls the latch function. When xLEAB is  
LOW, the latches are transparent. A subsequent LOW-to-  
HIGH transition of xLEAB signal puts the A latches in the  
storage mode. xOEAB performs output enable function on the  
B port. Data flow from the B port to the A port is similar but  
requiresusingxCEBA,xLEBA,andxOEBAinputs.Flow-through  
organization of signal pins simplifies layout. All inputs are  
designed with hysteresis for improved noise margin.  
The FCT163543/A/C have series current limiting resistors.  
These offer low ground bounce, minimal undershoot, and  
controlled output fall times–reducing the need for external  
series terminating resistors.  
FUNCTIONAL BLOCK DIAGRAM  
1
OEBA  
CEBA  
2OEBA  
2CEBA  
1
1
LEBA  
2LEBA  
2OEAB  
2CEAB  
1
OEAB  
1
CEAB  
LEAB  
2LEAB  
1
C
C
D
2A1  
1A1  
2B1  
D
1B1  
C
D
C
D
TO 7 OTHER CHANNELS  
TO 7 OTHER CHANNELS  
3250 drw 01  
3250 drw 02  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
COMMERCIAL TEMPERATURE RANGE  
SEPTEMBER 1996  
1996 Integrated Device Technology, Inc.  
8.7  
DSC-3250/2  
1
1234567

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