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IDT74FCT163501APA8 PDF预览

IDT74FCT163501APA8

更新时间: 2024-09-15 20:55:11
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
7页 74K
描述
Registered Bus Transceiver, FCT Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, TSSOP-56

IDT74FCT163501APA8 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP-56
针数:56Reach Compliance Code:not_compliant
风险等级:5.83其他特性:WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
控制类型:INDEPENDENT CONTROL计数方向:BIDIRECTIONAL
系列:FCTJESD-30 代码:R-PDSO-G56
JESD-609代码:e0长度:14 mm
负载电容(CL):50 pF逻辑集成电路类型:REGISTERED BUS TRANSCEIVER
最大I(ol):0.024 A湿度敏感等级:1
位数:18功能数量:1
端口数量:2端子数量:56
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP56,.3,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):240电源:3/3.3 V
Prop。Delay @ Nom-Sup:5.1 ns传播延迟(tpd):5.6 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
翻译:N/A触发器类型:POSITIVE EDGE
宽度:6.1 mmBase Number Matches:1

IDT74FCT163501APA8 数据手册

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3.3V CMOS 18-BIT  
IDT74FCT163501A/C  
REGISTERED TRANSCEIVER  
DESCRIPTION:  
FEATURES:  
TheFCT16350118-bitregisteredtransceiversarebuiltusingadvanced  
dual metal CMOS technology. These high-speed, low-power 18-bit  
registeredbustransceiverscombineD-typelatchesandD-typeflip-flopsto  
allowdataflowintransparent,latchedandclockedmodes. Dataflowineach  
direction is controlled by output-enable (OEAB and OEBA), latch enable  
(LEAB and LEBA) and clock (CLKAB and CLKBA) inputs. For A-to-B data  
flow, the device operates in transparent mode when LEAB is high. When  
LEABislow,theAdataislatchedifCLKABisheldatahighorlowlogiclevel.  
IfLEABislow,theAbusdataisstoredinthelatch/flip-floponthelow-to-high  
transitionofCLKAB. OEABperformstheoutputenablefunctionontheBport.  
Data flow from B port to A port is similiar but requires using OEBA, LEBA  
andCLKBA. Flow-throughorganizationofsignalpinssimplifieslayout. All  
inputs are designed with hysteresis for improved noise margin.  
• 0.5 MICRON CMOS Technology  
• Typical tSK(o) (Output Skew) < 250ps  
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using  
machine model (C = 200pF, R = 0)  
• VCC = 3.3V ± 0.3V, Normal Range, or VCC = 2.7V to 3.6V, Extended  
Range  
• CMOS power levels (0.4µ W typ. static)  
• Rail-to-rail output swing for increased noise margin  
• Low Ground Bounce (0.3V typ.)  
• Inputs (except I/O) can be driven by 3.3V or 5V components  
• Available in SSOP, TSSOP, and TVSOP packages  
The FCT163501 has series current limiting resistors. These offer low  
ground bounce, minimal undershoot, and controlled output fall times-  
reducing the need for external series terminating resistors.  
FUNCTIONALBLOCKDIAGRAM  
1
OEAB  
30  
CLKBA  
28  
LEBA  
27  
OEBA  
55  
CLKAB  
2
LEAB  
C
C
54  
B1  
3
D
A1  
D
C
D
C
D
TO 17 OTHER CHANNELS  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
APRIL 2002  
1
© 2002 Integrated Device Technology, Inc.  
DSC-2776/6  

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