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IDT74ALVCH16652PV PDF预览

IDT74ALVCH16652PV

更新时间: 2024-11-26 20:37:59
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
8页 180K
描述
Registered Bus Transceiver, ALVC/VCX/A Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, SSOP-56

IDT74ALVCH16652PV 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SSOP包装说明:SSOP, SSOP56,.4
针数:56Reach Compliance Code:not_compliant
风险等级:5.91其他特性:WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
控制类型:INDEPENDENT CONTROL计数方向:BIDIRECTIONAL
系列:ALVC/VCX/AJESD-30 代码:R-PDSO-G56
JESD-609代码:e0长度:18.415 mm
逻辑集成电路类型:REGISTERED BUS TRANSCEIVER最大I(ol):0.024 A
湿度敏感等级:1位数:8
功能数量:2端口数量:2
端子数量:56最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP56,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
电源:3.3 VProp。Delay @ Nom-Sup:5.2 ns
传播延迟(tpd):7.3 ns认证状态:Not Qualified
座面最大高度:2.794 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
翻译:N/A触发器类型:POSITIVE EDGE
宽度:7.5 mmBase Number Matches:1

IDT74ALVCH16652PV 数据手册

 浏览型号IDT74ALVCH16652PV的Datasheet PDF文件第2页浏览型号IDT74ALVCH16652PV的Datasheet PDF文件第3页浏览型号IDT74ALVCH16652PV的Datasheet PDF文件第4页浏览型号IDT74ALVCH16652PV的Datasheet PDF文件第5页浏览型号IDT74ALVCH16652PV的Datasheet PDF文件第6页浏览型号IDT74ALVCH16652PV的Datasheet PDF文件第7页 
3.3V CMOS 16-BIT BUS  
TRANSCEIVER AND  
IDT74ALVCH16652  
REGISTER WITH 3-STATE  
OUTPUTS AND BUS-HOLD  
FEATURES:  
directly from the data bus or from the internal storage registers. The  
device can be used as two 8-bit transceivers or one 16-bit transceiver.  
Complementary output enable (OEAB and OEBA) inputs are pro-  
vided to control the transceiver functions. Select control (SAB and SBA)  
inputs are provided to select whether real-time or stored data is  
transferred. A low input level selects real-time data, and a high input level  
selects stored data. Circuitry used for select control eliminates the typical  
decoding glitch that occurs in a multiplexer during the transition between  
stored and real-time data. Data on the A or B bus, or both, can be stored  
in the internal D flip-flops by low-to-high transition at the appropriate clock  
(CLKAB or CLKBA) inputs regardless of the levels on the select control  
or output enable inputs. When SAB and SBA are in the real-time transfer  
mode, it also is possible to store data without using the internal D-type  
flip-flops by simultaneously enabling OEAB and OEBA. In this configu-  
ration, each output reinforces its input. Thus, when all other data sources  
to the two sets of bus lines are in the high-impedance state, each set of  
bus lines remains at its last level configuration.  
0.5 MICRON CMOS Technology  
Typical tSK(0) (Output Skew) < 250ps  
ESD > 2000V per MIL-STD-883, Method 3015;  
> 200V using machine model (C = 200pF, R = 0)  
0.635mm pitch SSOP, 0.50mm pitch TSSOP,  
and 0.40mm pitch TVSOP packages  
Extended commercial range of – 40°C to + 85°C  
VCC = 3.3V ± 0.3V, Normal Range  
VCC = 2.7V to 3.6V, Extended Range  
VCC = 2.5V ± 0.2V  
CMOS power levels (0.4µW typ. static)  
Rail-to-Rail output swing for increased noise margin  
Drive Features for ALVCH16652:  
High Output Drivers: ±24mA  
Suitable for heavy loads  
APPLICATIONS:  
3.3V High Speed Systems  
3.3V and lower voltage computing systems  
The ALVCH16652 has been designed with a ±24mA output driver.  
This driver is capable of driving a moderate to heavy load while  
maintaining speed performance.  
The ALVCH16652 has bus-hold” which retains the inputs’ last state  
whenever the input bus goes to a high impedance. This prevents floating  
inputs and eliminates the need for pull-up/down resistors.  
DESCRIPTION:  
This 16-bit bus transceiver and register is built using advanced dual  
metal CMOS technology. The ALVCH16652 consists of D-type flip-flops  
and control circuitry arranged for multiplexed transmission of data  
FUNCTIONALBLOCKDIAGRAM  
56  
29  
1OEBA  
2OEBA  
1
28  
1OEAB  
2OEAB  
55  
30  
1CLKBA  
2CLKBA  
54  
31  
1SBA  
2SBA  
2
27  
1CLKAB  
2CLKAB  
3
26  
1SAB  
2SAB  
B REG  
B REG  
D
C
D
C
5
15  
52  
42  
1A1  
2A1  
A REG  
1B1  
A REG  
2B1  
D
D
C
C
TO 7 OTHER CHANNELS  
TO 7 OTHER CHANNELS  
EXTENDED COMMERCIAL TEMPERATURE RANGE  
OCTOBER 1999  
1
c
1999 Integrated Device Technology, Inc.  
DSC-4526/-  

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