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IDT74ALVCH16821PA8 PDF预览

IDT74ALVCH16821PA8

更新时间: 2024-11-26 14:42:47
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
6页 108K
描述
Bus Driver, ALVC/VCX/A Series, 2-Func, 10-Bit, True Output, CMOS, PDSO56, 0.50 MM PITCH, TSSOP-56

IDT74ALVCH16821PA8 技术参数

生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP,针数:56
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.45系列:ALVC/VCX/A
JESD-30 代码:R-PDSO-G56JESD-609代码:e0
长度:14 mm逻辑集成电路类型:BUS DRIVER
位数:10功能数量:2
端口数量:2端子数量:56
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟(tpd):5.3 ns认证状态:Not Qualified
座面最大高度:1.2 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL宽度:6.1 mm
Base Number Matches:1

IDT74ALVCH16821PA8 数据手册

 浏览型号IDT74ALVCH16821PA8的Datasheet PDF文件第2页浏览型号IDT74ALVCH16821PA8的Datasheet PDF文件第3页浏览型号IDT74ALVCH16821PA8的Datasheet PDF文件第4页浏览型号IDT74ALVCH16821PA8的Datasheet PDF文件第5页浏览型号IDT74ALVCH16821PA8的Datasheet PDF文件第6页 
3.3V CMOS 20-BIT  
IDT74ALVCH16821  
BUS-INTERFACE FLIP-FLOP  
WITH 3-STATE OUTPUTS  
AND BUS-HOLD  
FEATURES:  
DESCRIPTION:  
This high speed, 20-bit bus-interface flip-flop is built using advanced  
0.5 MICRON CMOS Technology  
Typical tSK(0) (Output Skew) < 250ps  
ESD > 2000V per MIL-STD-883, Method 3015;  
> 200V using machine model (C = 200pF, R = 0)  
0.635mm pitch SSOP, 0.50mm pitch TSSOP,  
and 0.40mm pitch TVSOP packages  
CMOS technology. The ALVCH16821 device can be used as two 10-bit  
flip-flops or one 20-bit flip-flop. On the positive transition of the clock  
(CLK) input, the device provides true data at the Q outputs.  
A buffered output-enable (OE) input can be used to place the ten  
outputs in either a normal logic state (high or low logic levels) or a high-  
impedance state. In the high impedance state, the outputs neither load  
nor drive the bus lines significantly. The high-impedance state and  
increased drive provide the capability to drive bus lines without the need  
for interface or pullup components. OE input does not affect the internal  
operation of the flip-flops. Old data can be retained or new data can be  
entered while the outputs are in the high-impedance state.  
Extended commercial range of – 40°C to + 85°C  
VCC = 3.3V ± 0.3V, Normal Range  
VCC = 2.7V to 3.6V, Extended Range  
VCC = 2.5V ± 0.2V  
CMOS power levels (0.4µW typ. static)  
Rail-to-Rail output swing for increased noise margin  
Drive Features for ALVCH16821:  
High Output Drivers: ±24mA  
Suitable for heavy loads  
The ALVCH16821 has been designed with a ±24mA output driver.  
This driver is capable of driving a moderate to heavy load while  
maintaining speed performance.  
APPLICATIONS:  
• 3.3V High Speed Systems  
• 3.3V and lower voltage computing systems  
The ALVCH16821 has bus-hold” which retains the inputs’ last state  
whenever the input goes to a high impedance. This prevents floating  
inputs and eliminates the need for pull-up/down resistor.  
FUNCTIONAL BLOCK DIAGRAM  
28  
1
2OE  
1OE  
29  
42  
56  
2CLK  
1CLK  
C1  
1D  
C1  
1D  
2
15  
2Q1  
1Q1  
55  
2D  
1
1D1  
One of 10  
Channels  
One of 10  
Channels  
TO NINE OTHER CHANNELS  
TO NINE OTHER CHANNELS  
EXTENDED COMMERCIAL TEMPERATURE RANGE  
AUGUST1999  
1
c 1999 Integrated Device Technology, Inc.  
DSC-4547/1  

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