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IDT74ALVCH16823PF8 PDF预览

IDT74ALVCH16823PF8

更新时间： 2024-11-26 20:08:39
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路电视
页数 文件大小 规格书
7页 111K
描述
Bus Driver, ALVC/VCX/A Series, 2-Func, 9-Bit, True Output, CMOS, PDSO56, 0.40 MM PITCH, TVSOP-56

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IDT74ALVCH16823PF8 技术参数

生命周期：Obsolete零件包装代码：SSOP
包装说明：TSSOP,针数：56
Reach Compliance Code：unknown风险等级：5.73
其他特性：WITH CLEAR AND CLOCK ENABLE系列：ALVC/VCX/A
JESD-30 代码：R-PDSO-G56JESD-609代码：e0
长度：11.3 mm逻辑集成电路类型：BUS DRIVER
位数：9功能数量：2
端口数量：2端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟（tpd）：5.2 ns认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：TIN LEAD
端子形式：GULL WING端子节距：0.4 mm
端子位置：DUAL宽度：4.4 mm
Base Number Matches：1

IDT74ALVCH16823PF8 数据手册

 浏览型号IDT74ALVCH16823PF8的Datasheet PDF文件第2页浏览型号IDT74ALVCH16823PF8的Datasheet PDF文件第3页浏览型号IDT74ALVCH16823PF8的Datasheet PDF文件第4页浏览型号IDT74ALVCH16823PF8的Datasheet PDF文件第5页浏览型号IDT74ALVCH16823PF8的Datasheet PDF文件第6页浏览型号IDT74ALVCH16823PF8的Datasheet PDF文件第7页 
3.3V CMOS 18-BIT  
IDT74ALVCH16823  
BUS-INTERFACE FLIP-FLOP  
WITH 3-STATE OUTPUTS  
AND BUS-HOLD  
registers, I/O ports, bidirectional bus drivers with parity, and working  
registers.  
FEATURES:  
–
–
–
0.5 MICRON CMOS Technology  
TypicaltSK(0) (Output Skew) < 250ps  
ESD > 2000V per MIL-STD-883, Method 3015;  
> 200V using machine model (C = 200pF, R = 0)  
0.635mm pitch SSOP, 0.50mm pitch TSSOP,  
and 0.40mm pitch TVSOP packages  
The ALVCH16823 can be used as two 9-bit flip-flops or one 18-bit flip-  
flop. With the clock-enable (CLKEN) input low, the D-type flip-flops enter  
data on the low-to-high transitions of the clock. Taking CLKEN high  
disables the clock buffer, thus latching the outputs. Taking the clear  
(CLR) input low causes the Q outputs to go low independently of the  
clock.  
–
–
–
–
–
–
–
Extended commercial range of – 40°C to + 85°C  
VCC = 3.3V ± 0.3V, Normal Range  
VCC = 2.7V to 3.6V, Extended Range  
VCC = 2.5V ± 0.2V  
CMOS power levels (0.4µW typ. static)  
Rail-to-Rail output swing for increased noise margin  
A buffered output-enable (OE) input can be used to place the nine  
outputs in either a normal logic state (high or low logic levels) or a high-  
impedance state. In the high-impedance state, the outputs neither load  
nor drive the bus lines significantly. The high-impedance state and  
increased drive provide the capability to drive bus lines without need for  
interface or pullup components. The output-enable (OE) input does not  
affect the internal operation of the flip-flops. Old data can be retained or  
new data can be entered while the outputs are in the high-impedance  
state.  
Drive Features for ALVCH16823:  
–
–
High Output Drivers: ±24mA  
Suitable for heavy loads  
APPLICATIONS:  
• 3.3V High Speed Systems  
• 3.3V and lower voltage computing systems  
The ALVCH16823 has been designed with a ±24mA output driver.  
This driver is capable of driving a moderate to heavy load while  
maintaining speed performance.  
DESCRIPTION:  
This 18-bit bus-interface flip-flop is built using advanced dual metal  
CMOS technology. The ALVCH16823 features 3-state outputs designed  
specifically for driving highly capacitive or relatively low-impedance  
loads. The device is particularly suitable for implementing wider buffer  
The ALVCH16823 has “bus-hold” which retains the inputs’ last state  
whenever the input goes to a high impedance. This prevents floating  
inputs and eliminates the need for pull-up/down resistor.  
Functional Block Diagram  
2
27  
2OE  
1OE  
1
28  
1CLR  
2CLR  
55  
30  
CE  
R
CE  
R
1CLKEN  
2CLKEN  
56  
54  
29  
42  
15  
3
1CLK  
1D1  
1Q1  
2CLK  
2D1  
2Q1  
C1  
C1  
D1  
D1  
TO 8 OTHER CHANNELS  
TO 8 OTHER CHANNELS  
EXTENDED COMMERCIAL TEMPERATURE RANGE  
APRIL 1999  
1
c
1999 Integrated Device Technology, Inc.  
DSC-4237/-  
1234567

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IDT74ALVCH16825PF8 IDT

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IDT74ALVCH16825PV8 IDT

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IDT74ALVCH16827PA8 IDT

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IDT74ALVCH16827PF8 IDT

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