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IDT74ALVCH16701PA8 PDF预览

IDT74ALVCH16701PA8

更新时间: 2024-11-23 21:02:47
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片光电二极管
页数 文件大小 规格书
8页 149K
描述
FIFO, 4X18, 5.5ns, Synchronous, CMOS, PDSO56, 0.50 MM PITCH, TSSOP-56

IDT74ALVCH16701PA8 技术参数

生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP,针数:56
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.84
最长访问时间:5.5 ns其他特性:CAN ALSO BE OPERATED AT 2.5V+/-0.2V
周期时间:12 nsJESD-30 代码:R-PDSO-G56
JESD-609代码:e0长度:14 mm
内存密度:72 bit内存宽度:18
功能数量:1端子数量:56
字数:4 words字数代码:4
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:4X18
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH并行/串行:PARALLEL
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
宽度:6.1 mmBase Number Matches:1

IDT74ALVCH16701PA8 数据手册

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IDT74ALVCH16701  
3.3V CMOS 18-BIT  
READ/WRITE BUFFER  
WITH BUS-HOLD  
FEATURES:  
DESCRIPTION:  
0.5 MICRON CMOS Technology  
Typical tSK(0) (Output Skew) < 250ps  
This 18-bit read/write buffer is built using advanced dual metal CMOS  
technology. The ALVCH16701 is equipped with a four deep FIFO and  
a read-back latch. It can be used as a read/write buffer between a CPU  
and a memory or to interface a high-speed bus and a slow peripheral.  
The A-to-B (write) path has a four deep FIFO for pipelined operations.  
The FIFO can be reset and a FIFO full condition is indicated by the full  
flag (FF). The B-to-A (read) path has a latch.  
ESD > 2000V per MIL-STD-883, Method 3015;  
> 200V using machine model (C = 200pF, R = 0)  
0.635mm pitch SSOP, 0.50mm pitch TSSOP,  
and 0.40mm pitch TVSOP packages  
Extended commercial range of – 40°C to + 85°C  
VCC = 3.3V ± 0.3V, Normal Range  
VCC = 2.7V to 3.6V, Extended Range  
VCC = 2.5V ± 0.2V  
CMOS power levels (0.4µW typ. static)  
Rail-to-Rail output swing for increased noise margin  
The ALVCH16701 has been designed with a ±24mA output driver.  
This driver is capable of driving a moderate to heavy load while  
maintaining speed performance.  
The ALVCH16701 has bus-hold” which retains the inputs’ last state  
whenever the input goes to a high impedance. This prevents floating  
inputs and eliminates the need for pull-up/down resistor.  
Drive Features for ALVCH16701:  
High Output Drivers: ±24mA  
Suitable for heavy loads  
APPLICATIONS:  
3.3V High Speed Systems  
3.3V and lower voltage computing systems  
FUNCTIONAL BLOCK DIAGRAM  
A1:18  
18  
27  
OEBA  
29  
RESET  
55  
CLK  
2
56  
30  
FIFO  
(4 deep)  
28  
WCE  
LATCH  
LE  
RCE  
FF  
1
OEAB  
18  
B1:18  
EXTENDEDCOMMERCIALTEMPERATURERANGE  
1
SEPTEMBER 1999  
c
1999 Integrated Device Technology, Inc.  
DSC-4222/-  

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