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IDT74ALVCH16245PV8 PDF预览

IDT74ALVCH16245PV8

更新时间: 2024-09-10 21:10:55
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管逻辑集成电路
页数 文件大小 规格书
6页 130K
描述
Bus Transceiver, ALVC/VCX/A Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, SSOP-48

IDT74ALVCH16245PV8 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SSOP包装说明:SSOP,
针数:48Reach Compliance Code:compliant
风险等级:5.22其他特性:WITH DIRECTION CONTROL
系列:ALVC/VCX/AJESD-30 代码:R-PDSO-G48
长度:15.875 mm逻辑集成电路类型:BUS TRANSCEIVER
位数:8功能数量:2
端口数量:2端子数量:48
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED传播延迟(tpd):3.7 ns
认证状态:Not Qualified座面最大高度:2.794 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.493 mmBase Number Matches:1

IDT74ALVCH16245PV8 数据手册

 浏览型号IDT74ALVCH16245PV8的Datasheet PDF文件第2页浏览型号IDT74ALVCH16245PV8的Datasheet PDF文件第3页浏览型号IDT74ALVCH16245PV8的Datasheet PDF文件第4页浏览型号IDT74ALVCH16245PV8的Datasheet PDF文件第5页浏览型号IDT74ALVCH16245PV8的Datasheet PDF文件第6页 
3.3V CMOS 16-BIT BUS  
TRANSCEIVER WITH  
IDT74ALVCH16245  
3-STATE OUTPUTS  
AND BUS-HOLD  
DESCRIPTION:  
FEATURES:  
0.5 MICRON CMOS Technology  
TypicaltSK(0) (Output Skew) < 250ps  
This 16-bit bus transceiver is built using advanced dual metal CMOS  
technology. The ALVCH16245 is designed for asynchronous commu-  
nication between data buses. The control-function implementation  
minimizes external timing requirements.  
ESD > 2000V per MIL-STD-883, Method 3015;  
> 200V using machine model (C = 200pF, R = 0)  
0.635mm pitch SSOP, 0.50mm pitch TSSOP,  
and 0.40mm pitch TVSOP packages  
Extended commercial range of – 40°C to + 85°C  
VCC = 3.3V ± 0.3V, Normal Range  
VCC = 2.7V to 3.6V, Extended Range  
VCC = 2.5V ± 0.2V  
CMOS power levels (0.4µW typ. static)  
This device can be used as two 8-bit transceivers or one 16-bit  
transceiver. It allows data transmission from the A bus to the B bus or  
from the B bus to the A bus, depending on the logic level at the direction-  
control (DIR) input. The output-enable (OE) input can be used to disable  
the device so that the buses are effectively isolated.  
Rail-to-Rail output swing for increased noise margin  
The ALVCH16245 has been designed with a ±24mA output driver.  
This driver is capable of driving a moderate to heavy load while  
maintaining speed performance.  
Drive Features for ALVCH16245:  
High Output Drivers: ±24mA  
Suitable for heavy loads  
The ALVCH16245 has bus-hold” which retains the inputs’ last state  
whenever the input bus goes to a high impedance. This prevents floating  
inputs and eliminates the need for pull-up/down resistors.  
APPLICATIONS:  
3.3V High Speed Systems  
3.3V and lower voltage computing systems  
Functional Block Diagram  
1
24  
1DIR  
2DIR  
48  
2
25  
13  
OE  
OE  
2
1
47  
36  
35  
33  
32  
30  
1A1  
2A1  
B
1
1
B
2
1
46  
1A2  
2A2  
2A3  
3
14  
16  
17  
1B2  
1B3  
2B2  
44  
1A3  
5
B
2
3
43  
A
A
2 4  
1
4
6
1B4  
2B4  
2B5  
2B6  
41  
40  
38  
1A5  
2A5  
2A6  
8
19  
20  
22  
B
5
1
29  
27  
A
1
6
9
B
6
1
1A7  
1A8  
A
2
7
11  
B
7
1
2B7  
2B8  
37  
26  
2A8  
12  
23  
1B8  
EXTENDED COMMERCIAL TEMPERATURE RANGE  
MARCH1999  
1
c
1999 Integrated Device Technology, Inc.  
DSC-4697/-  

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