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IDT74ALVCH162525PA8 PDF预览

IDT74ALVCH162525PA8

更新时间： 2024-09-10 21:09:07
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管逻辑集成电路
页数 文件大小 规格书
7页 132K
描述
Registered Bus Transceiver, ALVC/VCX/A Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, 0.50 MM PITCH, TSSOP-56

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IDT74ALVCH162525PA8 技术参数

生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP,针数：56
Reach Compliance Code：unknown风险等级：5.63
其他特性：WITH CLOCK ENABLE FOR EACH REGISTER系列：ALVC/VCX/A
JESD-30 代码：R-PDSO-G56JESD-609代码：e0
长度：14 mm逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
位数：18功能数量：1
端口数量：2端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE WITH SERIES RESISTOR输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟（tpd）：5.5 ns认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：TIN LEAD端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
宽度：6.1 mmBase Number Matches：1

IDT74ALVCH162525PA8 数据手册

 浏览型号IDT74ALVCH162525PA8的Datasheet PDF文件第2页浏览型号IDT74ALVCH162525PA8的Datasheet PDF文件第3页浏览型号IDT74ALVCH162525PA8的Datasheet PDF文件第4页浏览型号IDT74ALVCH162525PA8的Datasheet PDF文件第5页浏览型号IDT74ALVCH162525PA8的Datasheet PDF文件第6页浏览型号IDT74ALVCH162525PA8的Datasheet PDF文件第7页 
3.3V CMOS 18-BIT REGIS-  
TERED BUS TRANSCEIVER  
IDT74ALVCH162525  
WITH 3-STATE OUTPUTS  
AND BUS-HOLD  
FEATURES:  
metal CMOS technology. Data flow in each direction is controlled by  
output-enable (OEAB and OEBA) and clock-enable (CLKENAB and  
–
–
–
0.5 MICRON CMOS Technology  
TypicaltSK(0) (Output Skew) < 250ps  
ESD > 2000V per MIL-STD-883, Method 3015;  
> 200V using machine model (C = 200pF, R = 0)  
0.635mm pitch SSOP, 0.50mm pitch TSSOP,  
and 0.40mm pitch TVSOP packages  
CLKENBA) inputs. For the A-to-B data flow, the data flows through a  
single register. The B-to-A data can flow through a four-stage pipeline  
register path, or through a single register path, depending on the state  
of the select (SEL) input. Data is stored in the internal registers on the low-  
to-high transition of the clock (CLK) input, provided that the appropriate  
CLKEN inputs are low. The A-to-B data transfer is synchronized to the  
CLKAB input, and B-to-A data transfer is synchronized with the CLK1BA  
and CLK2BA inputs.  
–
–
–
–
–
–
–
Extended commercial range of – 40°C to + 85°C  
VCC = 3.3V ± 0.3V, Normal Range  
VCC = 2.7V to 3.6V, Extended Range  
VCC = 2.5V ± 0.2V  
CMOS power levels (0.4µW typ. static)  
Rail-to-Rail output swing for increased noise margin  
The ALVCH162525 has series resistors in the device output structure  
ofthe “B”portwhichwillsignificantlyreduce line noise whenusedwithlight  
loads. This driver has been designed to drive ±12mA at the designated  
threshold levels. The “A” port has a ±24mA driver.  
Drive Features for ALVCH162525:  
–
–
High Output Drivers: ±24mA (A port)  
Balanced Output Drivers: ±12mA (B port)  
To ensure the high-impedance state during power up or power down,  
OE should be tied to VCC through a pullup resistor; the minimum value  
of the resistor is determined by the current-sinking capability of the  
driver.  
APPLICATIONS:  
• 3.3V High Speed Systems  
• 3.3V and lower voltage computing systems  
The ALVCH162525 has “bus-hold” which retains the inputs’ last state  
whenever the input bus goes to a high impedance. This prevents floating  
inputs and eliminates the need for pull-up/down resistors.  
DESCRIPTION:  
This 18-bit registered bus transceiver is built using advanced dual  
Functional Block Diagram  
55  
CLK AB  
30  
CLK1BA  
29  
CLK2BA  
28  
CLKENBA  
1
CLKENAB  
2
OEAB  
27  
OEBA  
56  
SEL  
CE  
CE  
C1  
CE  
C1  
1D  
CE  
1
0
C1  
1D  
C1  
1D  
3
A1  
54  
1D  
B1  
CE  
C1  
1D  
1 of 18 Channels  
To 17 Other Channels  
EXTENDED COMMERCIAL TEMPERATURE RANGE  
MARCH1999  
1
c
1999 Integrated Device Technology, Inc.  
DSC-4220/-  
1234567

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