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IDT72V36100L15PF PDF预览

IDT72V36100L15PF

更新时间: 2024-09-11 23:01:15
品牌 Logo 应用领域
艾迪悌 - IDT 存储内存集成电路先进先出芯片时钟
页数 文件大小 规格书
36页 563K
描述
3.3 VOLT HIGH-DENSITY SUPERSYNC⑩ II 36-BIT FIFO

IDT72V36100L15PF 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:PLASTIC, TQFP-128针数:128
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.21
最长访问时间:10 ns其他特性:RETRANSMIT; AUTO POWER DOWN; ASYNCHRONOUS MODE IS ALSO POSSIBLE
最大时钟频率 (fCLK):66.7 MHz周期时间:15 ns
JESD-30 代码:R-PQFP-G128JESD-609代码:e0
长度:20 mm内存密度:2359296 bit
内存集成电路类型:OTHER FIFO内存宽度:36
湿度敏感等级:3功能数量:1
端子数量:128字数:65536 words
字数代码:64000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:64KX36可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP128,.63X.87,20封装形状:RECTANGULAR
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:3.3 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.015 A子类别:FIFOs
最大压摆率:0.06 mA最大供电电压 (Vsup):3.45 V
最小供电电压 (Vsup):3.15 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
宽度:14 mmBase Number Matches:1

IDT72V36100L15PF 数据手册

 浏览型号IDT72V36100L15PF的Datasheet PDF文件第2页浏览型号IDT72V36100L15PF的Datasheet PDF文件第3页浏览型号IDT72V36100L15PF的Datasheet PDF文件第4页浏览型号IDT72V36100L15PF的Datasheet PDF文件第5页浏览型号IDT72V36100L15PF的Datasheet PDF文件第6页浏览型号IDT72V36100L15PF的Datasheet PDF文件第7页 
3.3 VOLT HIGH-DENSITY SUPERSYNC™ II 36-BIT FIFO  
1,024 x 36, 2,048 x 36  
IDT72V3640,IDT72V3650  
IDT72V3660,IDT72V3670  
IDT72V3680, IDT72V3690  
IDT72V36100,IDT72V36110  
4,096 x 36, 8,192 x 36  
16,384 x 36, 32,768 x 36  
65,536 x36, 131,072 x 36  
Zero latency retransmit  
Auto power down minimizes standby power consumption  
Master Reset clears entire FIFO  
Partial Reset clears data, but retains programmable settings  
Empty, Full and Half-Full flags signal FIFO status  
Programmable Almost-Empty and Almost-Full flags, each flag can  
default to one of eight preselected offsets  
Selectable synchronous/asynchronous timing modes for Almost-  
Empty and Almost-Full flags  
Program programmable flags by either serial or parallel means  
Select IDT Standard timing (using EF and FF flags) or First Word  
Fall Through timing (using OR and IR flags)  
Output enable puts data outputs into high impedance state  
Easily expandable in depth and width  
Independent Read and Write Clocks (permit reading and writing  
simultaneously)  
Available in the 128-pin Thin Quad Flat Pack (TQFP)  
High-performance submicron CMOS technology  
Industrial temperature range (–40°C to +85°C) is available  
FEATURES:  
Choose among the following memory organizations:Commercial  
IDT72V3640  
IDT72V3650  
IDT72V3660  
IDT72V3670  
IDT72V3680  
IDT72V3690  
IDT72V36100  
IDT72V36110  
1,024 x 36  
2,048 x 36  
4,096 x 36  
8,192 x 36  
16,384 x 36  
32,768 x 36  
65,536 x 36  
131,072 x 36  
133 MHz operation (7.5 ns read/write cycle time)  
User selectable input and output port bus-sizing  
- x36 in to x36 out  
- x36 in to x18 out  
- x36 in to x9 out  
- x18 in to x36 out  
- x9 in to x36 out  
Big-Endian/Little-Endian user selectable byte representation  
5V input tolerant  
Fixed, low first word latency  
FUNCTIONALBLOCKDIAGRAM  
D0 -Dn (x36, x18 or x9)  
LD SEN  
WEN  
WCLK  
INPUT REGISTER  
OFFSET REGISTER  
FF/IR  
PAF  
EF/OR  
PAE  
HF  
FLAG  
LOGIC  
WRITE CONTROL  
LOGIC  
FWFT/SI  
PFM  
RAM ARRAY  
1,024 x 36, 2,048 x 36  
4,096 x 36, 8,192 x 36  
16,384 x 36, 32,768 x 36  
65,536 x 36, 131,072 x36  
FSEL0  
FSEL1  
WRITE POINTER  
READ POINTER  
BE  
CONTROL  
LOGIC  
IP  
READ  
CONTROL  
LOGIC  
RT  
RM  
BM  
IW  
OW  
OUTPUT REGISTER  
BUS  
CONFIGURATION  
MRS  
PRS  
RESET  
LOGIC  
RCLK  
REN  
4667 drw 01  
Q0 -Qn (x36, x18 or x9)  
OE  
The SuperSync II FIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
APRIL 2001  
1
2001 Integrated Device Technology, Inc.  
DSC-4667/3  

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