Datasheet > IDT72V36100L75PF

IDT72V36100L75PF

更新时间： 2024-09-14 22:07:47

品牌	Logo	应用领域
艾迪悌 - IDT		先进先出芯片
页数	文件大小	规格书
36页	563K
描述
3.3 VOLT HIGH-DENSITY SUPERSYNC⑩ II 36-BIT FIFO

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中文翻译

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IDT72V36100L75PF 数据手册

3.3 VOLT HIGH-DENSITY SUPERSYNC™ II 36-BIT FIFO

1,024 x 36, 2,048 x 36

IDT72V3640,IDT72V3650

IDT72V3660,IDT72V3670

IDT72V3680, IDT72V3690

IDT72V36100,IDT72V36110

4,096 x 36, 8,192 x 36

16,384 x 36, 32,768 x 36

65,536 x36, 131,072 x 36

• Zero latency retransmit

• Auto power down minimizes standby power consumption

• Master Reset clears entire FIFO

• Partial Reset clears data, but retains programmable settings

• Empty, Full and Half-Full flags signal FIFO status

• Programmable Almost-Empty and Almost-Full flags, each flag can

default to one of eight preselected offsets

• Selectable synchronous/asynchronous timing modes for Almost-

Empty and Almost-Full flags

• Program programmable flags by either serial or parallel means

• Select IDT Standard timing (using EF and FF flags) or First Word

Fall Through timing (using OR and IR flags)

• Output enable puts data outputs into high impedance state

• Easily expandable in depth and width

• Independent Read and Write Clocks (permit reading and writing

simultaneously)

• Available in the 128-pin Thin Quad Flat Pack (TQFP)

• High-performance submicron CMOS technology

• Industrial temperature range (–40°C to +85°C) is available

FEATURES:

• Choose among the following memory organizations:Commercial

IDT72V3640

IDT72V3650

IDT72V3660

IDT72V3670

IDT72V3680

IDT72V3690

IDT72V36100

IDT72V36110

1,024 x 36

2,048 x 36

4,096 x 36

8,192 x 36

16,384 x 36

32,768 x 36

65,536 x 36

131,072 x 36

• 133 MHz operation (7.5 ns read/write cycle time)

• User selectable input and output port bus-sizing

- x36 in to x36 out

- x36 in to x18 out

- x36 in to x9 out

- x18 in to x36 out

- x9 in to x36 out

• Big-Endian/Little-Endian user selectable byte representation

• 5V input tolerant

• Fixed, low first word latency

FUNCTIONALBLOCKDIAGRAM

D0 -Dn (x36, x18 or x9)

LD SEN

WEN

WCLK

INPUT REGISTER

OFFSET REGISTER

FF/IR

PAF

EF/OR

PAE

FLAG

LOGIC

WRITE CONTROL

LOGIC

FWFT/SI

PFM

RAM ARRAY

1,024 x 36, 2,048 x 36

4,096 x 36, 8,192 x 36

16,384 x 36, 32,768 x 36

65,536 x 36, 131,072 x36

FSEL0

FSEL1

WRITE POINTER

READ POINTER

CONTROL

LOGIC

READ

CONTROL

LOGIC

OUTPUT REGISTER

BUS

CONFIGURATION

MRS

PRS

RESET

LOGIC

RCLK

REN

4667 drw 01

Q0 -Qn (x36, x18 or x9)

The SuperSync II FIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

APRIL 2001

2001 Integrated Device Technology, Inc.

DSC-4667/3

12 3 4 5 6 7...36

中文翻译

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与IDT72V36100L75PF相关器件

型号	品牌	获取价格	描述	数据表
IDT72V36100L7-5PF8	IDT	获取价格	FIFO, 64KX36, 5ns, Synchronous, CMOS, PQFP128, PLASTIC, TQFP-128
IDT72V36100L7-5PFG	IDT	获取价格	FIFO, 64KX36, 5ns, Synchronous, CMOS, PQFP128, GREEN, PLASTIC, TQFP-128
IDT72V36100L7-5PFG8	IDT	获取价格	FIFO, 64KX36, 5ns, Synchronous, CMOS, PQFP128, PLASTIC, TQFP-128
IDT72V36100L7-5PFGI	IDT	获取价格	FIFO, 64KX36, 5ns, Synchronous, CMOS, PQFP128, GREEN, PLASTIC, TQFP-128
IDT72V36102	IDT	获取价格	3.3 VOLT CMOS SyncBiFIFO-TM
IDT72V36102L10PF	IDT	获取价格	3.3 VOLT CMOS SyncBiFIFO-TM
IDT72V36102L10PF9	IDT	获取价格	FIFO, 64KX36, 6.5ns, Synchronous, CMOS, PQFP120, TQFP-120
IDT72V36102L10PFG	IDT	获取价格	FIFO, 64KX36, 6.5ns, Synchronous, CMOS, PQFP120, TQFP-120
IDT72V36102L10PFG8	IDT	获取价格	FIFO, 64KX36, 6.5ns, Synchronous, CMOS, PQFP120, TQFP-120
IDT72V36102L15PF	IDT	获取价格	3.3 VOLT CMOS SyncBiFIFO-TM

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