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IDT72V02L15J PDF预览

IDT72V02L15J

更新时间: 2024-11-06 22:57:23
品牌 Logo 应用领域
艾迪悌 - IDT 存储内存集成电路先进先出芯片时钟
页数 文件大小 规格书
12页 142K
描述
3.3 VOLT CMOS ASYNCHRONOUS FIFO

IDT72V02L15J 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:QFJ
包装说明:PLASTIC, LCC-32针数:32
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.42
Is Samacsys:N最长访问时间:15 ns
最大时钟频率 (fCLK):50 MHz周期时间:25 ns
JESD-30 代码:R-PQCC-J32JESD-609代码:e0
长度:13.9954 mm内存密度:9216 bit
内存集成电路类型:OTHER FIFO内存宽度:9
湿度敏感等级:1功能数量:1
端子数量:32字数:1024 words
字数代码:1000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:1KX9可输出:NO
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC32,.5X.6封装形状:RECTANGULAR
封装形式:CHIP CARRIER并行/串行:PARALLEL
峰值回流温度(摄氏度):225电源:3.3 V
认证状态:Not Qualified座面最大高度:3.556 mm
子类别:FIFOs最大压摆率:0.05 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:20宽度:11.4554 mm
Base Number Matches:1

IDT72V02L15J 数据手册

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3.3 VOLT CMOS ASYNCHRONOUS FIFO  
512 x 9, 1,024 x 9,  
2,048 x 9, 4,096 x 9,  
IDT72V01, IDT72V02  
IDT72V03, IDT72V04  
IDT72V05, IDT72V06  
8,192 x 9, 16,384 x 9  
FEATURES:  
DESCRIPTION:  
3.3V family uses less power than the 5 Volt 7201/7202/7203/7204/  
7205/7206family  
512 x 9 organization (72V01)  
1,024 x 9 organization (72V02)  
2,048 x 9 organization (72V03)  
4,096 X 9 organization (72V04)  
8,192 x 9 organization (72V05)  
16,384 X 9 organization (72V06)  
Functionally compatible with 720x family  
Low-power consumption  
Active: 180 mW (max.)  
— Power-down: 18 mW (max.)  
15 ns access time  
Asynchronous and simultaneous read and write  
Fully expandable by both word depth and/or bit width  
Status Flags: Empty, Half-Full, Full  
Auto-retransmit capability  
The IDT72V01/72V02/72V03/72V04/72V05/72V06 are dual-port FIFO  
memoriesthatoperateatapowersupplyvoltage(Vcc)between3.0Vand3.6V.  
Theirarchitecture,functionaloperationandpinassignmentsareidenticalto  
those ofthe IDT7201/7202/7203/7204/7205/7206. These devices loadand  
emptydataonafirst-in/first-outbasis.TheyuseFullandEmptyflagstoprevent  
data overflow and underflow and expansion logic to allow for unlimited  
expansioncapabilityinbothwordsize anddepth.  
The reads and writes are internally sequential through the use of ring  
pointers,withnoaddressinformationrequiredtoloadandunloaddata.Data  
istoggledinandoutofthedevicesthroughtheuseoftheWrite(W)andRead  
(R)pins. The devices have a maximumdata access time as fastas 25ns.  
Thedevicesutilizea9-bitwidedataarraytoallowforcontrolandparitybits  
attheusersoption.Thisfeatureisespeciallyusefulindatacommunications  
applicationswhereitisnecessarytouseaparitybitfortransmission/reception  
errorchecking.TheyalsofeatureaRetransmit(RT)capabilitythatallowsfor  
resetofthereadpointertoitsinitialpositionwhenRTispulsedLOWtoallowfor  
retransmissionfromthebeginningofdata.AHalf-FullFlagisavailableinthe  
singledevicemodeandwidthexpansionmodes.  
Available in 32-pin PLCC  
Industrial temperature range (–40  
°
C to +85  
°
C) is available  
TheseFIFOsarefabricatedusingIDT’shigh-speedCMOStechnology.It  
hasbeendesignedforthoseapplicationsrequiringasynchronousandsimul-  
taneousread/writesinmultiprocessingandratebufferapplications.  
FUNCTIONAL BLOCK DIAGRAM  
DATA INPUTS  
(D0-D8)  
WRITE  
CONTROL  
W
RAM  
ARRAY  
512 x 9  
1,024 x 9  
2,048 x 9  
4,096 x 9  
8,192 x 9  
16,384 x 9  
WRITE  
POINTER  
READ  
POINTER  
THREE-  
STATE  
BUFFERS  
RS  
DATA OUTPUTS  
READ  
CONTROL  
(Q0-Q8)  
RESET  
LOGIC  
R
FLAG  
LOGIC  
EF  
FF  
FL/RT  
EXPANSION  
LOGIC  
XI  
XO/HF  
3033 drw 01  
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc  
MAY 2003  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-3033/3  

IDT72V02L15J 替代型号

型号 品牌 替代类型 描述 数据表
72V02L15JG8 IDT

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