Datasheet > IDT72T54262

IDT72T54262

更新时间： 2024-09-17 03:59:47

品牌	Logo	应用领域
艾迪悌 - IDT		先进先出芯片双倍数据速率
页数	文件大小	规格书
56页	544K
描述
2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS

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中文翻译

获取价格

数据手册

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IDT72T54262 数据手册

2.5VQUAD/DUALTeraSync™DDR/SDRFIFO

x10QUADFIFOorx10/x20DUALFIFOCONFIGURATIONS

32,768 x 10 x 4/16,384 x 20 x 2

65,536 x 10 x 4/32,768 x 20 x 2

131,072 x 10 x 4/65,536 x 20 x 2

IDT72T54242

IDT72T54252

IDT72T54262

•

Up to 200MHz operating frequency or 2Gbps throughput in SDR mode

Up to 100MHz operating frequency or 2Gbps throughput in DDR mode

Double Data Rate, DDR is selectable, providing up to 400Mbps

bandwidth per data pin

User selectable Single or Double Data Rate modes on both the

write port(s) and read port(s)

FEATURES

•

Choose from among the following memory organizations:

IDT72T54242

IDT72T54252

IDT72T54262

32,768 x 10 x 4/32,768 x 10 x 2

65,536 x 10 x 4/65,536 x 10 x 2

131,072 x 10 x 4/131,072 x 10 x 2

•

User Selectable Quad / Dual Mode - Choose between two or

four independent FIFOs

Quad Mode offers

•

All I/Os are LVTTL/ HSTL/ eHSTL user selectable

3.3V tolerant inputs in LVTTL mode

ERCLK and EREN Echo outputs on all read ports

Write enable WEN and Chip Select WCS input for each write port

Read enable REN and Chip Select RCS input for each read port

User Selectable IDT Standard mode (using EF and FF) or FWFT

mode (using IR and OR)

Programmable Almost Empty and Almost Full flags per FIFO

Dedicated Serial Port for flag offset programming

Power Down pin minimizes power consumption

2.5V Supply Voltage

Available in a 324-pin PBGA, 1mm pitch, 19mm x 19mm

IEEE 1149.1 compliant JTAG port provides boundary scan function

Low Power, High Performance CMOS technology

Industrial temperature range (-40°C to +85°C)

- Eight discrete clock domain, (four write clocks & four read clocks)

- Four separate write ports, write data to four independent FIFOs

- 10-bit wide write ports

- Four separate read ports, read data from any of four independent FIFOs

- Independent set of status flags and control signals for each FIFO

Dual Mode offers

•

- Four discrete clock domain, (two write clocks & two read clocks)

- Two separate write ports, write data to two independent FIFOs

- 10-bit/20-bit wide write ports

- Two separate read ports, read data from any of two independent FIFOs

- Independent set of status flags and control signals for each FIFO

- Bus-Matching on read and write port x10/x20

- Maximum depth of each FIFO is the same as in Quad Mode

FUNCTIONALBLOCKDIAGRAMS

Quad Mode

RCLK0

REN0

RCS0

OE0

ERCLK0

EREN0

WCLK0

WEN0

WCS0

Data In D[9:0]

FIFO 0

Data Out

32,768 x 10

65,536 x 10

131,072 x 10

Q[9:0]

RCLK1

REN1

RCS1

OE1

x10

FIFO 0

WCLK1

WEN1

WCS1

ERCLK1

EREN1

FIFO 1

32,768 x 10

65,536 x 10

131,072 x 10

FIFO 1

Data Out

Data In D[19:10]

Q[19:10]

RCLK2

REN2

RCS2

OE2

x10

FIFO 1

WCLK2

WEN2

WCS2

ERCLK2

EREN2

FIFO 2

Data Out

32,768 x 10

65,536 x 10

131,072 x 10

Data In D[29:20]

Q[29:20]

RCLK3

REN3

RCS3

OE3

ERCLK3

EREN3

x10

FIFO 2

WCLK3

WEN3

WCS3

FIFO 3

Data In

FIFO 3

Data Out

32,768 x 10

65,536 x 10

131,072 x 10

D[39:30]

Q[39:30]

FIFO 3

EF0/OR0

PAE0

FF0/IR0

PAF0

FF1/IR1

PAF1

FF2/ IR2

PAF2

EF1/OR1

PAE1

EF2/OR2

PAE2

EF3/OR3

PAE3

FF3/IR3

PAF3

6158 drw01

(See next page for Dual Mode)

IDTandtheIDTlogoaretrademarksofIntegratedDeviceTechnology,Inc.TheTeraSyncisatrademarkofIntegratedDeviceTechnology,Inc.

MARCH 2005

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES



DSC-6158/3

12 3 4 5 6 7...56

中文翻译

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与IDT72T54262相关器件

型号	品牌	获取价格	描述	数据表
IDT72T54262L5BB	IDT	获取价格	2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUA
IDT72T54262L5BBG	IDT	获取价格	FIFO, 128KX20, 3.6ns, Synchronous, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324
IDT72T54262L5BBI	IDT	获取价格	2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUA
IDT72T54262L6-7BB	IDT	获取价格	FIFO, 128KX20, 3.8ns, Synchronous, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324
IDT72T54262L6-7BBG	IDT	获取价格	FIFO, 128KX20, 3.8ns, Synchronous, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324
IDT72T54262L6-7BBGI	IDT	获取价格	FIFO, 128KX20, 3.8ns, Synchronous, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324
IDT72T55248L5BBG	IDT	获取价格	FIFO, 32KX40, 3.6ns, Synchronous, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324
IDT72T55248L6-7BB	IDT	获取价格	FIFO, 32KX40, 3.8ns, Synchronous, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324
IDT72T55248L6-7BBG	IDT	获取价格	FIFO, 32KX40, 3.8ns, Synchronous, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324
IDT72T55248L6-7BBGI	IDT	获取价格	FIFO, 32KX40, 3.8ns, Synchronous, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324

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