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IDT72T55268L5BBG PDF预览

IDT72T55268L5BBG

更新时间： 2024-11-07 19:06:59
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
65页 592K
描述
FIFO, 128KX40, 3.6ns, Synchronous, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324

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IDT72T55268L5BBG 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：BGA
包装说明：19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324针数：324
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.32.00.71风险等级：5.84
最长访问时间：3.6 ns周期时间：5 ns
JESD-30 代码：S-PBGA-B324JESD-609代码：e1
长度：19 mm内存密度：5242880 bit
内存宽度：40湿度敏感等级：3
功能数量：1端子数量：324
字数：131072 words字数代码：128000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：128KX40
可输出：YES封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装形状：SQUARE
封装形式：GRID ARRAY并行/串行：PARALLEL
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：1.97 mm最大供电电压 (Vsup)：2.625 V
最小供电电压 (Vsup)：2.375 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：TIN SILVER COPPER
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：30
宽度：19 mmBase Number Matches：1

IDT72T55268L5BBG 数据手册

 浏览型号IDT72T55268L5BBG的Datasheet PDF文件第2页浏览型号IDT72T55268L5BBG的Datasheet PDF文件第3页浏览型号IDT72T55268L5BBG的Datasheet PDF文件第4页浏览型号IDT72T55268L5BBG的Datasheet PDF文件第5页浏览型号IDT72T55268L5BBG的Datasheet PDF文件第6页浏览型号IDT72T55268L5BBG的Datasheet PDF文件第7页 
2.5VQUADMUXDDRFLOW-CONTROLDEVICE  
WITHMUX/DEMUX/BROADCASTFUNCTIONS  
8,192 x 40 x 4  
IDT72T55248  
IDT72T55258  
IDT72T55268  
16,384 x 40 x 4  
32,768 x 40 x 4  
•
Demux Mode offers 1:4 architecture  
- Five discrete clock domains, one write clock and four read clocks  
FEATURES  
•
Choose from among the following memory organizations:  
IDT72T55248 - 8,192 words, 40-bits/word maximum, 4 Sequential  
Queues total  
- Four separate read ports, read data from four independent Queues  
- One single write port, capable of writing to any four Queues  
- Selectable single or double data rate on read and write ports  
- 10-bit wide read ports in single data rate, doubles internally in double  
data rate  
- 40-bit wide write port, doubles internally in double data rate,  
selectable between the four independent Queues  
- Bus Matching on the Write Port x10/x20/x40 (SDR/DDR)  
- Fully independent status flags for every Queue  
- Composite Full/Input Ready Flag monitors currently selected Queue  
- Dedicated partial reset for every Queue  
Broadcast Write Mode offers, 1:4 architecture (with simultaneous  
writes to all Queues)  
- Five discrete clock domains, one write clock and four read clocks  
- Four separate read ports, read data from four independent Queues  
- One single write port, writes to all four independent Queues  
simultaneously  
IDT72T55258 - 16,384 words, 40-bits/word maximum, 4 Sequential  
Queues total  
IDT72T55268 - 32,768 words, 40-bits/word maximum, 4 Sequential  
Queues total  
•
•
User Selectable Mux / Demux / Broadcast Write Modes  
Mux Mode offers 4:1 architecture  
- Five discrete clock domains, four write clocks and one read clock  
- Four separate write ports, writes data to four independent Queues  
- One single read port, capable of reading from any four Queues  
- Selectable single or double data rate (SDR/DDR) on read and write  
ports  
•
- 10-bit wide write ports in single data rate, doubles internally in double  
data rate  
- 40-bit wide read port, doubles internally in double data rate,  
selectable between the four independent Queues  
- Bus Matching on the Read Port x10/x20/x40 (SDR/DDR)  
- Fully independent status flags for every Queue  
- Composite Empty/OutputReadyFlagmonitors currentlyselected  
Queue  
- 10-bit wide read ports in single data rate, doubles internally in double  
data rate  
- 40-bit wide write port, doubles internally in double data rate  
- Selectable single or double data rate on read and write ports  
- Bus-Matching on the write port x10/x20/x40 (SDR/DDR)  
- Dedicated partial reset for every Queue  
FUNCTIONALBLOCKDIAGRAMS  
Mux Mode  
WCLK0  
RCLK0  
REN0  
RCS0  
WEN0  
WCS0  
D[9:0]  
Queue 0  
Data In  
8,192 x 40  
16,384 x40  
32,768 x 40  
10  
10  
10  
OE0  
Queue 0  
Queue 1  
WCLK1  
WEN1  
WCS1  
OS[1:0]  
2
Queue 1  
8,192 x 40  
16,384 x40  
32,768 x 40  
Data In D[19:10]  
x10,x20,x40  
WCLK2  
WEN2  
WCS2  
Data Out  
Q[39:0]  
Queue 2  
8,192 x 40  
16,384 x40  
32,768 x 40  
Data In D[29:20]  
Queue 2  
Queue 3  
WCLK3  
WEN3  
WCS3  
Queue 3  
Data In  
8,192 x 40  
16,384 x40  
32,768 x 40  
D[39:30]  
10  
EF0/OR0  
PAE0  
EF1/OR1  
FF0/IR0  
PAF0  
FF1/IR1  
PAE1  
PAF1  
FF2/ IR2  
PAF2  
FF3/IR3  
PAF3  
EF2/OR2  
PAE2  
EF3/OR3  
PAE3  
CEF/COR  
6157 drw01  
(See next pages for Demux and Broadcast modes)  
IDTandtheIDTlogoaretrademarksofIntegratedDeviceTechnology,Inc  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
MARCH 2005  
1
2005 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-6157/4  
1234567...65

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与IDT72T55268L5BBG相关器件

型号 品牌 获取价格 描述 数据表
IDT72T55268L6-7BBGI IDT

获取价格

 		FIFO, 128KX40, 3.8ns, Synchronous, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324
IDT72T55268L6-7BBI IDT

获取价格

 		FIFO, 128KX40, 3.8ns, Synchronous, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324
IDT72T6360L6BB IDT

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 		Microprocessor Circuit, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324
IDT72T6360L6BBG IDT

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 		Microprocessor Circuit, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324
IDT72T6360L6BBI IDT

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 		Microprocessor Circuit, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324
IDT72T6360L7.5BB IDT

获取价格

 		Microprocessor Circuit, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324
IDT72T6360L7.5BBG IDT

获取价格

 		Microprocessor Circuit, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324
IDT72T6360L7.5BBGI IDT

获取价格

 		Microprocessor Circuit, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324
IDT72T6360L7.5BBI IDT

获取价格

 		Microprocessor Circuit, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324
IDT72T6360L7-5BBG IDT

获取价格

 		Microprocessor Circuit, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324

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