Datasheet > 存储 > SRAM> IDT70V37L15PFI

IDT70V37L15PFI

更新时间： 2024-10-28 03:55:59

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
17页	155K
描述
HIGH-SPEED 3.3V 32K x 18 DUAL- STATIC RAM

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中文翻译

获取价格

数据手册

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IDT70V37L15PFI 数据手册

PRELIMINARY

IDT70V37L

HIGH-SPEED 3.3V

32K x 18 DUAL-PORT

STATIC RAM

ꢀeatures

◆

True Dual-Ported memory cells which allow simultaneous

access of the same memory location

High-speed access

– Commercial:15/20ns (max.)

– Industrial:20ns (max.)

M/S = VIH for BUSY output flag on Master,

M/S = VIL for BUSY input on Slave

Busy and Interrupt Flags

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

◆

Low-power operation

◆

– IDT70V37L

Fully asynchronous operation from either port

Separate upper-byte and lower-byte controls for multi-

plexed bus and bus matching compatibility

LVTTL-compatible, single 3.3V (±0.3V) power supply

Available in a 100-pin TQFP

Active:440mW(typ.)

Standby: 660µW (typ.)

Dual chip enables allow for depth expansion without

external logic

IDT70V37 easily expands data bus width to 36 bits or

more using the Master/Slave select when cascading more

than one device

◆

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

ꢀunctional Block Diagram

R/WL

UBL

R/WR

UB_R

CE0L

CE_0R

CE_1L

CE_1R

OE_R

OEL

LBL

LBR

I/O 9-17L

I/O 0-8L

I/O9-17R

I/O

Control

I/O

Control

I/O0-8R

(1,2)

BUSYR

BUSYL

32Kx18

MEMORY

ARRAY

70V37

14L

A14R

Address

Decoder

Address

Decoder

A0L

A0R

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

CE0R

CE1R

CE0L

CE1L

OEL

OER

R/WR

R/WL

SEM_L

INT_L

SEM_R

(2)

INTR

M/S⁽¹⁾

NOTES:

4851 drw 01

1. BUSY is an input as a Slave (M/S=V^IL) and an output when it is a Master (M/S=VIH).

2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).

JANUARY 2002

DSC-4851/2

12 3 4 5 6 7...17

中文翻译

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