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IDT70V37L20PFGI PDF预览

IDT70V37L20PFGI

更新时间: 2024-10-28 12:58:27
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
17页 155K
描述
Dual-Port SRAM, 32KX18, 20ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100

IDT70V37L20PFGI 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:QFP
包装说明:LFQFP,针数:100
Reach Compliance Code:compliantECCN代码:3A991.B.2.B
HTS代码:8542.32.00.41风险等级:5.54
Is Samacsys:N最长访问时间:20 ns
其他特性:INTERRUPT FLAGJESD-30 代码:S-PQFP-G100
JESD-609代码:e3长度:14 mm
内存密度:589824 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:18湿度敏感等级:3
功能数量:1端子数量:100
字数:32768 words字数代码:32000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:32KX18
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:14 mm
Base Number Matches:1

IDT70V37L20PFGI 数据手册

 浏览型号IDT70V37L20PFGI的Datasheet PDF文件第2页浏览型号IDT70V37L20PFGI的Datasheet PDF文件第3页浏览型号IDT70V37L20PFGI的Datasheet PDF文件第4页浏览型号IDT70V37L20PFGI的Datasheet PDF文件第5页浏览型号IDT70V37L20PFGI的Datasheet PDF文件第6页浏览型号IDT70V37L20PFGI的Datasheet PDF文件第7页 
PRELIMINARY  
IDT70V37L  
HIGH-SPEED 3.3V  
32K x 18 DUAL-PORT  
STATIC RAM  
ꢀeatures  
True Dual-Ported memory cells which allow simultaneous  
access of the same memory location  
High-speed access  
– Commercial:15/20ns (max.)  
Industrial:20ns (max.)  
M/S = VIH for BUSY output flag on Master,  
M/S = VIL for BUSY input on Slave  
Busy and Interrupt Flags  
On-chip port arbitration logic  
Full on-chip hardware support of semaphore signaling  
between ports  
Low-power operation  
IDT70V37L  
Fully asynchronous operation from either port  
Separate upper-byte and lower-byte controls for multi-  
plexed bus and bus matching compatibility  
LVTTL-compatible, single 3.3V (±0.3V) power supply  
Available in a 100-pin TQFP  
Active:440mW(typ.)  
Standby: 660µW (typ.)  
Dual chip enables allow for depth expansion without  
external logic  
IDT70V37 easily expands data bus width to 36 bits or  
more using the Master/Slave select when cascading more  
than one device  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
ꢀunctional Block Diagram  
R/WL  
UBL  
R/WR  
UBR  
CE0L  
CE0R  
CE1L  
CE1R  
OER  
OEL  
LBL  
LBR  
I/O 9-17L  
I/O 0-8L  
I/O9-17R  
I/O  
Control  
I/O  
Control  
I/O0-8R  
(1,2)  
(1,2)  
BUSYR  
BUSYL  
.
32Kx18  
MEMORY  
ARRAY  
70V37  
14L  
A14R  
A
Address  
Decoder  
Address  
Decoder  
A0L  
A0R  
15  
15  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE0R  
CE1R  
CE0L  
CE1L  
OEL  
OER  
R/WR  
R/WL  
SEML  
INTL  
SEMR  
(2)  
(2)  
INTR  
M/S(1)  
NOTES:  
4851 drw 01  
1. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).  
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).  
JANUARY 2002  
1
DSC-4851/2  
©2002IntegratedDeviceTechnology,Inc.  

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