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IDT70V27L35PFI PDF预览

IDT70V27L35PFI

更新时间: 2024-10-27 22:35:43
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
22页 192K
描述
HIGH-SPEED 3.3V 32K x 16 DUAL-PORT STATIC RAM

IDT70V27L35PFI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:14 X 14 MM, 1.40 MM HEIGHT, TQFP-100针数:100
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.41
最长访问时间:35 ns其他特性:INTERRUPT FLAGS
I/O 类型:COMMONJESD-30 代码:S-PQFP-G100
JESD-609代码:e0长度:14 mm
内存密度:524288 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:16湿度敏感等级:3
功能数量:1端口数量:2
端子数量:100字数:32768 words
字数代码:32000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:32KX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP100,.63SQ,20封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:3.3 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.006 A最小待机电流:3 V
子类别:SRAMs最大压摆率:0.235 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:20宽度:14 mm
Base Number Matches:1

IDT70V27L35PFI 数据手册

 浏览型号IDT70V27L35PFI的Datasheet PDF文件第2页浏览型号IDT70V27L35PFI的Datasheet PDF文件第3页浏览型号IDT70V27L35PFI的Datasheet PDF文件第4页浏览型号IDT70V27L35PFI的Datasheet PDF文件第5页浏览型号IDT70V27L35PFI的Datasheet PDF文件第6页浏览型号IDT70V27L35PFI的Datasheet PDF文件第7页 
HIGH-SPEED 3.3V  
32K x 16 DUAL-PORT  
STATIC RAM  
IDT70V27S/L  
Features:  
IDT70V27 easily expands data bus width to 32 bits or more  
using the Master/Slave select when cascading more than  
one device  
M/S = VIH for BUSY output flag on Master,  
M/S = VIL for BUSY input on Slave  
Busy and Interrupt Flags  
On-chip port arbitration logic  
Full on-chip hardware support of semaphore signaling  
between ports  
Fully asynchronous operation from either port  
LVTTL-compatible, single 3.3V (±0.3V) power supply  
Available in 100-pin Thin Quad Flatpack (TQFP), 108-pin  
Ceramic Pin Grid Array (PGA), and 144-pin Fine Pitch BGA  
(fpBGA)  
True Dual-Ported memory cells which allow simultaneous  
access of the same memory location  
High-speed access  
Industrial:35ns (max.)  
– Commercial:15/20/25/35/55ns(max.)  
Low-power operation  
IDT70V27S  
Active:500mW(typ.)  
Standby: 3.3mW (typ.)  
IDT70V27L  
Active:500mW(typ.)  
Standby:660µW(typ.)  
Separate upper-byte and lower-byte control for bus  
matching capability  
Dual chip enables allow for depth expansion without  
Industrial temperature range (-40°C to +85°C) is available  
for selected speeds  
external logic  
FunctionalBlockDiagram  
R/WL  
UBL  
R/WR  
UBR  
CE0L  
CE0R  
CE1L  
CE1R  
OER  
LBR  
OEL  
LBL  
I/O8-15L  
I/O0-7L  
I/O8-15R  
I/O0-7R  
I/O  
Control  
I/O  
Control  
(1,2)  
(1,2)  
BUSY  
L
BUSYR  
32Kx16  
A14R  
A14L  
A0L  
Address  
Decoder  
Address  
Decoder  
MEMORY  
ARRAY  
70V27  
A0R  
A14L  
A14R  
A0R  
CE0R  
A0L  
CE0L  
CE1L  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE1R  
OER  
OEL  
R/WL  
R/WR  
L
L
SEM  
INT  
SEMR  
(2)  
(2)  
INTR  
M/S(2)  
NOTES:  
3603 drw 01  
1) BUSY is an input as a Slave (M/S=VIL) and an output as a Master (M/S=VIH).  
2) BUSY and INT are non-tri-state totem-pole outputs (push-pull).  
JANUARY 2001  
6.011  
DSC 3603/7  
©2000IntegratedDeviceTechnology,Inc.  

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