5秒后页面跳转
IDT70V27S15BFGI PDF预览

IDT70V27S15BFGI

更新时间: 2024-10-28 13:08:39
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
22页 192K
描述
暂无描述

IDT70V27S15BFGI 数据手册

 浏览型号IDT70V27S15BFGI的Datasheet PDF文件第2页浏览型号IDT70V27S15BFGI的Datasheet PDF文件第3页浏览型号IDT70V27S15BFGI的Datasheet PDF文件第4页浏览型号IDT70V27S15BFGI的Datasheet PDF文件第5页浏览型号IDT70V27S15BFGI的Datasheet PDF文件第6页浏览型号IDT70V27S15BFGI的Datasheet PDF文件第7页 
HIGH-SPEED 3.3V  
32K x 16 DUAL-PORT  
STATIC RAM  
IDT70V27S/L  
Features:  
IDT70V27 easily expands data bus width to 32 bits or more  
using the Master/Slave select when cascading more than  
one device  
M/S = VIH for BUSY output flag on Master,  
M/S = VIL for BUSY input on Slave  
Busy and Interrupt Flags  
On-chip port arbitration logic  
Full on-chip hardware support of semaphore signaling  
between ports  
Fully asynchronous operation from either port  
LVTTL-compatible, single 3.3V (±0.3V) power supply  
Available in 100-pin Thin Quad Flatpack (TQFP), 108-pin  
Ceramic Pin Grid Array (PGA), and 144-pin Fine Pitch BGA  
(fpBGA)  
True Dual-Ported memory cells which allow simultaneous  
access of the same memory location  
High-speed access  
Industrial:35ns (max.)  
– Commercial:15/20/25/35/55ns(max.)  
Low-power operation  
IDT70V27S  
Active:500mW(typ.)  
Standby: 3.3mW (typ.)  
IDT70V27L  
Active:500mW(typ.)  
Standby:660µW(typ.)  
Separate upper-byte and lower-byte control for bus  
matching capability  
Dual chip enables allow for depth expansion without  
Industrial temperature range (-40°C to +85°C) is available  
for selected speeds  
external logic  
FunctionalBlockDiagram  
R/WL  
UBL  
R/WR  
UBR  
CE0L  
CE0R  
CE1L  
CE1R  
OER  
LBR  
OEL  
LBL  
I/O8-15L  
I/O0-7L  
I/O8-15R  
I/O0-7R  
I/O  
Control  
I/O  
Control  
(1,2)  
(1,2)  
BUSY  
L
BUSYR  
32Kx16  
A14R  
A14L  
A0L  
Address  
Decoder  
Address  
Decoder  
MEMORY  
ARRAY  
70V27  
A0R  
A14L  
A14R  
A0R  
CE0R  
A0L  
CE0L  
CE1L  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE1R  
OER  
OEL  
R/WL  
R/WR  
L
L
SEM  
INT  
SEMR  
(2)  
(2)  
INTR  
M/S(2)  
NOTES:  
3603 drw 01  
1) BUSY is an input as a Slave (M/S=VIL) and an output as a Master (M/S=VIH).  
2) BUSY and INT are non-tri-state totem-pole outputs (push-pull).  
JANUARY 2001  
6.011  
DSC 3603/7  
©2000IntegratedDeviceTechnology,Inc.  

与IDT70V27S15BFGI相关器件

型号 品牌 获取价格 描述 数据表
IDT70V27S15BFI IDT

获取价格

HIGH-SPEED 3.3V 32K x 16 DUAL-PORT STATIC RAM
IDT70V27S15G IDT

获取价格

HIGH-SPEED 3.3V 32K x 16 DUAL-PORT STATIC RAM
IDT70V27S15GI IDT

获取价格

HIGH-SPEED 3.3V 32K x 16 DUAL-PORT STATIC RAM
IDT70V27S15PF IDT

获取价格

HIGH-SPEED 3.3V 32K x 16 DUAL-PORT STATIC RAM
IDT70V27S15PF8 IDT

获取价格

Dual-Port SRAM, 32KX16, 15ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100
IDT70V27S15PF9 IDT

获取价格

Dual-Port SRAM, 32KX16, 15ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100
IDT70V27S15PFGI IDT

获取价格

Dual-Port SRAM, 32KX16, 15ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100
IDT70V27S15PFI IDT

获取价格

HIGH-SPEED 3.3V 32K x 16 DUAL-PORT STATIC RAM
IDT70V27S20BF IDT

获取价格

HIGH-SPEED 3.3V 32K x 16 DUAL-PORT STATIC RAM
IDT70V27S20BFG IDT

获取价格

Dual-Port SRAM, 32KX16, 20ns, CMOS, PBGA144, 12 X 12 MM, 1.40 MM HEIGHT, GREEN, FBGA-144