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IDT70V27L55PF9 PDF预览

IDT70V27L55PF9

更新时间: 2024-10-28 15:34:43
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
21页 306K
描述
Dual-Port SRAM, 32KX16, 55ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100

IDT70V27L55PF9 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:14 X 14 MM, 1.40 MM HEIGHT, TQFP-100针数:100
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.41
最长访问时间:55 ns其他特性:INTERRUPT FLAGS
JESD-30 代码:S-PQFP-G100JESD-609代码:e0
长度:14 mm内存密度:524288 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:16
湿度敏感等级:3功能数量:1
端子数量:100字数:32768 words
字数代码:32000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:32KX16封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):240认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
宽度:14 mmBase Number Matches:1

IDT70V27L55PF9 数据手册

 浏览型号IDT70V27L55PF9的Datasheet PDF文件第2页浏览型号IDT70V27L55PF9的Datasheet PDF文件第3页浏览型号IDT70V27L55PF9的Datasheet PDF文件第4页浏览型号IDT70V27L55PF9的Datasheet PDF文件第5页浏览型号IDT70V27L55PF9的Datasheet PDF文件第6页浏览型号IDT70V27L55PF9的Datasheet PDF文件第7页 
HIGH-SPEED 3.3V  
32K x 16 DUAL-PORT  
STATIC RAM  
IDT70V27S/L  
Features:  
IDT70V27 easily expands data bus width to 32 bits or more  
using the Master/Slave select when cascading more than  
one device  
M/S = VIH for BUSY output flag on Master,  
M/S = VIL for BUSY input on Slave  
True Dual-Ported memory cells which allow simultaneous  
access of the same memory location  
High-speed access  
– Commercial:15/20/25/35/55ns(max.)  
– Industrial: 20/35ns(max.)  
Low-power operation  
Busy and Interrupt Flags  
On-chip port arbitration logic  
– IDT70V27S  
Full on-chip hardware support of semaphore signaling  
between ports  
Fully asynchronous operation from either port  
LVTTL-compatible, single 3.3V (±0.3V) power supply  
Available in 100-pin Thin Quad Flatpack (TQFP), and 144-  
pin Fine Pitch BGA (fpBGA)  
Active:500mW(typ.)  
Standby: 3.3mW (typ.)  
– IDT70V27L  
Active:500mW(typ.)  
Standby: 660µW (typ.)  
Separate upper-byte and lower-byte control for bus  
Industrial temperature range (-40°C to +85°C) is available  
for selected speeds  
matching capability  
Dual chip enables allow for depth expansion without  
external logic  
FunctionalBlockDiagram  
R/W  
L
R/WR  
UB  
L
UB  
R
CE0L  
CE0R  
CE1L  
CE1R  
OE  
R
OE  
L
L
LB  
R
LB  
I/O8-15L  
I/O0-7L  
I/O8-15R  
I/O0-7R  
I/O  
Control  
I/O  
Control  
,
(1,2)  
(1,2)  
BUSY  
L
BUSY  
R
32Kx16  
A
14R  
0R  
A
14L  
0L  
Address  
Decoder  
Address  
Decoder  
MEMORY  
ARRAY  
70V27  
A
A
A
14L  
A
A
CE0R  
14R  
0R  
A
CE0L  
0L  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE1L  
CE1R  
OE  
OE  
L
R
R/  
WL  
R/WR  
L
L
SEM  
INT  
SEM  
R
(2)  
(2)  
INT  
R
M/S(2)  
NOTES:  
3603 drw 01  
1) BUSY is an input as a Slave (M/S=VIL) and an output as a Master (M/S=VIH).  
2) BUSY and INT are non-tri-state totem-pole outputs (push-pull).  
AUGUST 2004  
6.01  
1
DSC 3603/8  
©2004IntegratedDeviceTechnology,Inc.  

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