Datasheet > 存储 > SRAM> IDT70T633S10DDI

IDT70T633S10DDI

更新时间： 2024-10-28 22:07:15

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
27页	340K
描述
HIGH-SPEED 2.5V 512/256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE

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中文翻译

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数据手册

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IDT70T633S10DDI 数据手册

HIGH-SPEED 2.5V

512/256K x 18

PRELIMINARY

IDT70T633/1S

ASYNCHRONOUS DUAL-PORT

STATIC RAM

WITH 3.3V 0R 2.5V INTERFACE

◆

Features

Full hardware support of semaphore signaling between

ports on-chip

On-chip port arbitration logic

Fully asynchronous operation from either port

Separate byte controls for multiplexed bus and bus

matching compatibility

Sleep Mode Inputs on both ports

Supports JTAG features compliant to IEEE 1149.1 in

BGA-208 and BGA-256 packages

Single 2.5V (±100mV) power supply for core

LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)

power supply for I/Os and control signals on each port

Available in a 256-ball Ball Grid Array, 144-pin Thin Quad

Flatpack and 208-ball fine pitch Ball Grid Array

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

◆

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed access

◆

– Commercial:8/10/12/15ns(max.)

– Industrial: 10/12ns(max.)

◆

RapidWrite Mode simplifies high-speed consecutive write

◆

cycles

◆

Dual chip enables allow for depth expansion without

external logic

◆

IDT70T633/1 easily expands data bus width to 36 bits or

more using the Master/Slave select when cascading more

than one device

◆

M/S = VIH for BUSY output flag on Master,

M/S = VIL for BUSY input on Slave

Busy and Interrupt Flags

◆

Functional Block Diagram

UBL

LBL

R/WL

R/WR

CE0L

CE0R

CE1L

CE1R

OEL

OER

Dout0-8_L

Dout9-17_L

Dout0-8_R

Dout9-17_R

512/256K x 18

MEMORY

ARRAY

Din_L

I/O0L- I/O17L

Din_R

I/O0R - I/O17R

(1)

18R

(1)

Address

Decoder

Address

Decoder

18L

ADDR_L

ADDR_R

TDI

TCK

TMS

TRST

JTAG

OER

ARBITRATION

TDO

INTERRUPT

SEMAPHORE

LOGIC

CE0R

CE1R

CE0L

CE1L

R/WL

R/W

(2,3)

BUSY

SEM

INT

BUSY

SEM

M/S

(3)

INT

CONTROL

LOGIC

(4)

ZZR

NOTES:

1. Address A18x is a NC for IDT70T631.

2. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).

5670 drw 01

BUSY and INT are non-tri-state totem-pole outputs (push-pull).

4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the

sleep mode pins themselves (ZZx) are not affected during sleep mode.

NOVEMBER 2003

DSC-5670/3

12 3 4 5 6 7...27

中文翻译

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与IDT70T633S10DDI相关器件

型号	品牌	获取价格	描述	数据表
IDT70T633S12BC	IDT	获取价格	HIGH-SPEED 2.5V 512/256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFAC
IDT70T633S12BC8	IDT	获取价格	Dual-Port SRAM, 512KX18, 12ns, CMOS, PBGA256, 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, BGA-
IDT70T633S12BCG8	IDT	获取价格	Multi-Port SRAM, 512KX18, 12ns, CMOS, PBGA256
IDT70T633S12BCGI8	IDT	获取价格	Multi-Port SRAM, 512KX18, 12ns, CMOS, PBGA256
IDT70T633S12BCI	IDT	获取价格	HIGH-SPEED 2.5V 512/256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFAC
IDT70T633S12BCI8	IDT	获取价格	Dual-Port SRAM, 512KX18, 12ns, CMOS, PBGA256, 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, BGA-
IDT70T633S12BF	IDT	获取价格	HIGH-SPEED 2.5V 512/256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFAC
IDT70T633S12BF8	IDT	获取价格	Dual-Port SRAM, 512KX18, 12ns, CMOS, PBGA208, 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, F
IDT70T633S12BFG	IDT	获取价格	Dual-Port SRAM, 512KX18, 12ns, CMOS, PBGA208, 15 X 15 MM, 1.40 MM HIEGHT, 0.80 MM, PITCH,
IDT70T633S12BFGI	IDT	获取价格	Dual-Port SRAM, 512KX18, 12ns, CMOS, PBGA208, 15 X 15 MM, 1.40 MM HIEGHT, 0.80 MM, PITCH,

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