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IDT70T633S12BCI8 PDF预览

IDT70T633S12BCI8

更新时间: 2024-10-29 21:21:11
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
27页 337K
描述
Dual-Port SRAM, 512KX18, 12ns, CMOS, PBGA256, 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, BGA-256

IDT70T633S12BCI8 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:BGA
包装说明:LBGA, BGA256,16X16,40针数:256
Reach Compliance Code:not_compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.22
最长访问时间:12 nsI/O 类型:COMMON
JESD-30 代码:S-PBGA-B256JESD-609代码:e0
长度:17 mm内存密度:9437184 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:18
湿度敏感等级:3功能数量:1
端口数量:2端子数量:256
字数:524288 words字数代码:512000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:512KX18
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LBGA封装等效代码:BGA256,16X16,40
封装形状:SQUARE封装形式:GRID ARRAY, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):225
电源:2.5,2.5/3.3 V认证状态:Not Qualified
座面最大高度:1.5 mm最大待机电流:0.02 A
最小待机电流:2.4 V子类别:SRAMs
最大压摆率:0.395 mA最大供电电压 (Vsup):2.6 V
最小供电电压 (Vsup):2.4 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn63Pb37)
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:20
宽度:17 mmBase Number Matches:1

IDT70T633S12BCI8 数据手册

 浏览型号IDT70T633S12BCI8的Datasheet PDF文件第2页浏览型号IDT70T633S12BCI8的Datasheet PDF文件第3页浏览型号IDT70T633S12BCI8的Datasheet PDF文件第4页浏览型号IDT70T633S12BCI8的Datasheet PDF文件第5页浏览型号IDT70T633S12BCI8的Datasheet PDF文件第6页浏览型号IDT70T633S12BCI8的Datasheet PDF文件第7页 
IDT70T633/1S  
HIGH-SPEED 2.5V  
512/256K x 18  
ASYNCHRONOUS DUAL-PORT  
STATIC RAM  
WITH 3.3V 0R 2.5V INTERFACE  
Features  
Full hardware support of semaphore signaling between  
ports on-chip  
True Dual-Port memory cells which allow simultaneous  
access of the same memory location  
High-speed access  
On-chip port arbitration logic  
Fully asynchronous operation from either port  
Separate byte controls for multiplexed bus and bus  
matching compatibility  
– Commercial:8/10/12/15ns(max.)  
– Industrial: 10/12ns(max.)  
RapidWrite Mode simplifies high-speed consecutive write  
Sleep Mode Inputs on both ports  
cycles  
Supports JTAG features compliant to IEEE 1149.1 in  
BGA-208 and BGA-256 packages  
Dual chip enables allow for depth expansion without  
external logic  
Single 2.5V (±100mV) power supply for core  
LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)  
power supply for I/Os and control signals on each port  
Available in a 256-ball Ball Grid Array, 144-pin Thin Quad  
Flatpack and 208-ball fine pitch Ball Grid Array  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
IDT70T633/1 easily expands data bus width to 36 bits or  
more using the Master/Slave select when cascading more  
than one device  
M/S = VIH for BUSY output flag on Master,  
M/S = VIL for BUSY input on Slave  
Busy and Interrupt Flags  
Functional Block Diagram  
UBL  
UB  
R
LBL  
LB  
R
R/WL  
R/WR  
B
E
0
L
B
E
1
L
B
E
1
B
E
0
CE0L  
CE0R  
R
R
CE1L  
CE1R  
OEL  
OER  
Dout0-8_L  
Dout9-17_L  
Dout0-8_R  
Dout9-17_R  
512/256K x 18  
MEMORY  
ARRAY  
Din_L  
I/O0L- I/O17L  
Din_R  
I/O0R - I/O17R  
(1)  
A
A
18R  
0R  
(1)  
Address  
Decoder  
Address  
Decoder  
A
18L  
ADDR_L  
ADDR_R  
A
0L  
TDI  
TCK  
TMS  
TRST  
JTAG  
OE  
L
OER  
ARBITRATION  
TDO  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE0R  
CE1R  
CE0L  
CE1L  
R/WL  
R/W  
R
(2,3)  
L
(2,3)  
R
BUSY  
SEM  
INT  
BUSY  
SEM  
M/S  
L
R
(3)  
(3)  
R
L
INT  
ZZ  
CONTROL  
LOGIC  
(4)  
(4)  
ZZR  
ZZ  
L
NOTES:  
1. Address A18x is a NC for IDT70T631.  
2. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).  
5670 drw 01  
3
BUSY and INT are non-tri-state totem-pole outputs (push-pull).  
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the  
sleep mode pins themselves (ZZx) are not affected during sleep mode.  
APRIL 2004  
1
DSC-5670/4  
©2004IntegratedDeviceTechnology,Inc.  

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