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IDT70T633S12DDI8

更新时间： 2024-11-26 05:58:27
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器
页数 文件大小 规格书
27页 227K
描述
Multi-Port SRAM, 512KX18, 12ns, CMOS, PQFP144

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IDT70T633S12DDI8 数据手册

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IDT70T633/1S  
HIGH-SPEED 2.5V  
512/256K x 18  
ASYNCHRONOUS DUAL-PORT  
STATIC RAM  
WITH 3.3V 0R 2.5V INTERFACE  
◆
Features  
Full hardware support of semaphore signaling between  
ports on-chip  
◆
True Dual-Port memory cells which allow simultaneous  
access of the same memory location  
High-speed access  
◆
◆
◆
On-chip port arbitration logic  
◆
Fully asynchronous operation from either port  
Separate byte controls for multiplexed bus and bus  
matching compatibility  
Sleep Mode Inputs on both ports  
Supports JTAG features compliant to IEEE 1149.1 in  
BGA-208 and BGA-256 packages  
Single 2.5V (±100mV) power supply for core  
LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)  
power supply for I/Os and control signals on each port  
Available in a 256-ball Ball Grid Array, 144-pin Thin Quad  
Flatpack and 208-ball fine pitch Ball Grid Array  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
– Commercial:8/10/12/15ns(max.)  
– Industrial:10/12ns (max.)  
◆
RapidWrite Mode simplifies high-speed consecutive write  
◆
◆
cycles  
◆
Dual chip enables allow for depth expansion without  
external logic  
◆
◆
◆
IDT70T633/1 easily expands data bus width to 36 bits or  
more using the Master/Slave select when cascading more  
than one device  
◆
◆
◆
◆
M/S = VIH for BUSY output flag on Master,  
M/S = VIL for BUSY input on Slave  
Busy and Interrupt Flags  
◆
Green parts available, see ordering information  
Functional Block Diagram  
UBL  
UB  
R
LBL  
LB  
R
R/WL  
R/WR  
B
E
0
L
B
E
1
L
B
E
1
B
E
0
CE0L  
CE0R  
R
R
CE1L  
CE1R  
OEL  
OER  
Dout0-8_L  
Dout9-17_L  
Dout0-8_R  
Dout9-17_R  
512/256K x 18  
MEMORY  
ARRAY  
Din_L  
I/O0L- I/O17L  
Din_R  
I/O0R - I/O17R  
(1)  
A
A
18R  
0R  
(1)  
Address  
Decoder  
Address  
Decoder  
A
18L  
ADDR_L  
ADDR_R  
A
0L  
TDI  
TCK  
TMS  
TRST  
JTAG  
OE  
L
OER  
ARBITRATION  
TDO  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE0R  
CE1R  
CE0L  
CE1L  
R/WL  
R/W  
R
(2,3)  
L
(2,3)  
R
BUSY  
SEM  
INT  
BUSY  
SEM  
M/S  
L
R
(3)  
(3)  
R
L
INT  
ZZ  
CONTROL  
LOGIC  
(4)  
(4)  
ZZR  
ZZ  
L
NOTES:  
1. Address A18x is a NC for IDT70T631.  
5670 drw 01  
2. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).  
BUSY and INT are non-tri-state totem-pole outputs (push-pull).  
3
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the  
sleep mode pins themselves (ZZx) are not affected during sleep mode.  
JANUARY 2006  
1
DSC-5670/5  
©2006IntegratedDeviceTechnology,Inc.  
1234567...27

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与IDT70T633S12DDI8相关器件

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IDT70T633S15BCG8 IDT

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 		HIGH-SPEED 2.5V 512/256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFAC
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IDT70T633S15BFG8 IDT

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 		Multi-Port SRAM, 512KX18, 15ns, CMOS, PBGA208
IDT70T633S15BFI IDT

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 		HIGH-SPEED 2.5V 512/256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFAC
IDT70T633S15DD IDT

获取价格

 		HIGH-SPEED 2.5V 512/256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFAC
IDT70T633S15DD8 IDT

获取价格

 		Multi-Port SRAM, 512KX18, 15ns, CMOS, PQFP144

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