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IDT707278S20PF9 PDF预览

IDT707278S20PF9

更新时间: 2024-11-14 15:34:43
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
16页 124K
描述
Dual-Port SRAM, 32KX16, 20ns, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100

IDT707278S20PF9 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:QFP,
针数:100Reach Compliance Code:compliant
ECCN代码:3A991.B.2.BHTS代码:8542.32.00.41
风险等级:5.92最长访问时间:20 ns
JESD-30 代码:S-PQFP-G100JESD-609代码:e0
长度:14 mm内存密度:524288 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:16
湿度敏感等级:3功能数量:1
端子数量:100字数:32768 words
字数代码:32000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:32KX16封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装形状:SQUARE
封装形式:FLATPACK并行/串行:PARALLEL
峰值回流温度(摄氏度):240认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
宽度:14 mmBase Number Matches:1

IDT707278S20PF9 数据手册

 浏览型号IDT707278S20PF9的Datasheet PDF文件第2页浏览型号IDT707278S20PF9的Datasheet PDF文件第3页浏览型号IDT707278S20PF9的Datasheet PDF文件第4页浏览型号IDT707278S20PF9的Datasheet PDF文件第5页浏览型号IDT707278S20PF9的Datasheet PDF文件第6页浏览型号IDT707278S20PF9的Datasheet PDF文件第7页 
HIGH-SPEED  
IDT707278S/L  
32K x 16 BANK-SWITCHABLE  
DUAL-PORTED SRAM WITH  
EXTERNAL BANK SELECTS  
Features  
32K x 16 Bank-Switchable Dual-Ported SRAM Architecture  
Four independent 8K x 16 banks  
Interrupt flags with programmable masking  
Dual Chip Enables allow for depth expansion without  
external logic  
UB and LB are available for x8 or x16 bus matching  
TTL-compatible, single 5V (±10%) power supply  
Available in a 100-pin Thin Quad Flatpack (14mm x 14mm)  
– 512 Kilobit of memory on chip  
Fast asynchronous address-to-data access time: 15ns  
User-controlled input pins included for bank selects  
Independent port controls with asynchronous address &  
data busses  
Four 16-bit mailboxes available to each port for inter-  
processor communications; interrupt option  
FunctionalBlockDiagram  
MUX  
R/W  
CE0L  
L
R/W  
CE0R  
CE1R  
R
8Kx16  
MEMORY  
ARRAY  
CONTROL  
LOGIC  
CONTROL  
LOGIC  
CE1L  
UB  
LB  
OE  
L
L
L
UB  
LB  
OE  
R
(BANK 0)  
R
R
MUX  
MUX  
I/O  
CONTROL  
I/O  
CONTROL  
I/O8L-15L  
I/O0L-7L  
I/O8R-15R  
I/O0R-7R  
8Kx16  
MEMORY  
ARRAY  
(BANK 1)  
A
12L  
A
12R  
ADDRESS  
DECODE  
ADDRESS  
DECODE  
(1)  
0L  
(1)  
0R  
A
A
MUX  
BA1R  
BA0R  
BA1L  
BA0L  
BANK  
DECODE  
BANK  
DECODE  
MUX  
8Kx16  
MEMORY  
ARRAY  
(BANK 3)  
MUX  
(2)  
(2)  
BKSEL  
3
BANK  
SELECT  
BKSEL  
0
(1)  
(1)  
(1)  
(1)  
A
A
5R  
0R  
A
A
5L  
0L  
MAILBOX  
INTERRUPT  
LOGIC  
LBR/UBR  
LB  
L
/UB  
OE  
R/W  
CE  
L
OE  
R
L
R/WR  
L
CE  
R
L
MBSEL  
L
MBSEL  
R
3739 drw 01  
INTL  
INTR  
NOTES:  
1. The first six address pins for each port serve dual functions. When MBSEL = VIH, the pins serve as memory address inputs. When MBSEL = VIL, the pins  
serve as mailbox address inputs.  
2. Each bank has an input pin assigned that allows the user to toggle the assignment of that bank between the two ports. Refer to Truth Table I for  
more details.  
MAY 2000  
1
DSC 3739/6  
©2000IntegratedDeviceTechnology,Inc.  

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