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IDT707278S25PF8 PDF预览

IDT707278S25PF8

更新时间: 2024-09-27 08:47:35
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器
页数 文件大小 规格书
16页 124K
描述
Dual-Port SRAM, 32KX16, 25ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100

IDT707278S25PF8 数据手册

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HIGH-SPEED  
IDT707278S/L  
32K x 16 BANK-SWITCHABLE  
DUAL-PORTED SRAM WITH  
EXTERNAL BANK SELECTS  
Features  
32K x 16 Bank-Switchable Dual-Ported SRAM Architecture  
Four independent 8K x 16 banks  
Interrupt flags with programmable masking  
Dual Chip Enables allow for depth expansion without  
external logic  
UB and LB are available for x8 or x16 bus matching  
TTL-compatible, single 5V (±10%) power supply  
Available in a 100-pin Thin Quad Flatpack (14mm x 14mm)  
– 512 Kilobit of memory on chip  
Fast asynchronous address-to-data access time: 15ns  
User-controlled input pins included for bank selects  
Independent port controls with asynchronous address &  
data busses  
Four 16-bit mailboxes available to each port for inter-  
processor communications; interrupt option  
FunctionalBlockDiagram  
MUX  
R/W  
CE0L  
L
R/W  
CE0R  
CE1R  
R
8Kx16  
MEMORY  
ARRAY  
CONTROL  
LOGIC  
CONTROL  
LOGIC  
CE1L  
UB  
LB  
OE  
L
L
L
UB  
LB  
OE  
R
(BANK 0)  
R
R
MUX  
MUX  
I/O  
CONTROL  
I/O  
CONTROL  
I/O8L-15L  
I/O0L-7L  
I/O8R-15R  
I/O0R-7R  
8Kx16  
MEMORY  
ARRAY  
(BANK 1)  
A
12L  
A
12R  
ADDRESS  
DECODE  
ADDRESS  
DECODE  
(1)  
0L  
(1)  
0R  
A
A
MUX  
BA1R  
BA0R  
BA1L  
BA0L  
BANK  
DECODE  
BANK  
DECODE  
MUX  
8Kx16  
MEMORY  
ARRAY  
(BANK 3)  
MUX  
(2)  
(2)  
BKSEL  
3
BANK  
SELECT  
BKSEL  
0
(1)  
(1)  
(1)  
(1)  
A
A
5R  
0R  
A
A
5L  
0L  
MAILBOX  
INTERRUPT  
LOGIC  
LBR/UBR  
LB  
L
/UB  
OE  
R/W  
CE  
L
OE  
R
L
R/WR  
L
CE  
R
L
MBSEL  
L
MBSEL  
R
3739 drw 01  
INTL  
INTR  
NOTES:  
1. The first six address pins for each port serve dual functions. When MBSEL = VIH, the pins serve as memory address inputs. When MBSEL = VIL, the pins  
serve as mailbox address inputs.  
2. Each bank has an input pin assigned that allows the user to toggle the assignment of that bank between the two ports. Refer to Truth Table I for  
more details.  
MAY 2000  
1
DSC 3739/6  
©2000IntegratedDeviceTechnology,Inc.  

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