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IDT707288L15PFG PDF预览

IDT707288L15PFG

更新时间: 2024-09-27 07:17:35
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器
页数 文件大小 规格书
16页 125K
描述
Dual-Port SRAM, 64KX16, 15ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM, TQFP-100

IDT707288L15PFG 数据手册

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HIGH-SPEED  
IDT707288S/L  
64K x 16 BANK-SWITCHABLE  
DUAL-PORTED SRAM WITH  
EXTERNAL BANK SELECTS  
Features  
64K x 16 Bank-Switchable Dual-Ported SRAM Architecture  
– Four independent 16K x 16 banks  
processor communications; interrupt option  
Interrupt flags with programmable masking  
Dual Chip Enables allow for depth expansion without  
external logic  
UB and LB are available for x8 or x16 bus matching  
TTL-compatible, single 5V (±10%) power supply  
Available in a 100-pin Thin Quad Flatpack (14mm x 14mm)  
– 1 Megabit of memory on chip  
Fast asynchronous address-to-data access time: 15ns  
User-controlled input pins included for bank selects  
Independent port controls with asynchronous address &  
data busses  
Four 16-bit mailboxes available to each port for inter-  
FunctionalBlockDiagram  
MUX  
R/W  
L
R/WR  
CE0L  
CE1L  
16Kx16  
MEMORY  
ARRAY  
CE0R  
CE1R  
CONTROL  
LOGIC  
CONTROL  
LOGIC  
UB  
LB  
OE  
L
L
L
UB  
LB  
OE  
R
(BANK 0)  
R
R
MUX  
MUX  
I/O  
CONTROL  
I/O  
CONTROL  
I/O8L-15L  
I/O0L-7L  
I/O8R-15R  
I/O0R-7R  
16Kx16  
MEMORY  
ARRAY  
(BANK 1)  
A
13L  
A
A
13R  
ADDRESS  
DECODE  
ADDRESS  
DECODE  
(1)  
(1)  
0R  
A0L  
MUX  
BA1R  
BA0R  
BA1L  
BA0L  
BANK  
DECODE  
BANK  
DECODE  
MUX  
16Kx16  
MEMORY  
ARRAY  
(BANK 3)  
MUX  
(2)  
(2)  
BKSEL  
BKSEL  
3
0
BANK  
SELECT  
(1)  
(1)  
(1)  
(1)  
A
A
5R  
0R  
A
A
5L  
0L  
MAILBOX  
INTERRUPT  
LOGIC  
LB  
OE  
R/W  
CE  
R/UB  
R
LB  
L
/UBL  
R
OEL  
R
R/W  
L
R
CEL  
MBSEL  
L
L
MBSEL  
R
INT  
INTR  
3592 drw 01  
NOTES:  
1. The first six address pins for each port serve dual functions. When MBSEL = VIH, the pins serve as memory address inputs. When MBSEL = VIL, the pins  
serve as mailbox address inputs.  
2. Each bank has an input pin assigned that allows the user to toggle the assignment of that bank between the two ports. Refer to Truth Table I for  
more details.  
MAY 2000  
1
DSC 3592/7  
©2000IntegratedDeviceTechnology,Inc.  

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