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IDT707288L20PFI PDF预览

IDT707288L20PFI

更新时间: 2024-09-26 04:58:19
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器
页数 文件大小 规格书
16页 138K
描述
HIGH-SPEED 64K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS

IDT707288L20PFI 数据手册

 浏览型号IDT707288L20PFI的Datasheet PDF文件第2页浏览型号IDT707288L20PFI的Datasheet PDF文件第3页浏览型号IDT707288L20PFI的Datasheet PDF文件第4页浏览型号IDT707288L20PFI的Datasheet PDF文件第5页浏览型号IDT707288L20PFI的Datasheet PDF文件第6页浏览型号IDT707288L20PFI的Datasheet PDF文件第7页 
HIGH-SPEED  
IDT707288S/L  
64K x 16 BANK-SWITCHABLE  
DUAL-PORTED SRAM WITH  
EXTERNAL BANK SELECTS  
Features  
64K x 16 Bank-Switchable Dual-Ported SRAM Architecture  
processor communications; interrupt option  
– Four independent 16K x 16 banks  
Interrupt flags with programmable masking  
Dual Chip Enables allow for depth expansion without  
external logic  
UB and LB are available for x8 or x16 bus matching  
TTL-compatible, single 5V (±10%) power supply  
Available in a 100-pin Thin Quad Flatpack (14mm x 14mm)  
– 1 Megabit of memory on chip  
Fast asynchronous address-to-data access time: 15ns  
User-controlled input pins included for bank selects  
Independent port controls with asynchronous address &  
data busses  
Four 16-bit mailboxes available to each port for inter-  
FunctionalBlockDiagram  
MUX  
R/WL  
R/WR  
CE0L  
16Kx16  
MEMORY  
ARRAY  
0R  
CE  
CONTROL  
LOGIC  
CONTROL  
LOGIC  
CE1L  
UBL  
LBL  
CE1R  
UBR  
LBR  
(BANK 0)  
OER  
OEL  
MUX  
MUX  
I/O  
CONTROL  
I/O  
CONTROL  
I/O8L-15L  
I/O0L-7L  
I/O8R-15R  
I/O0R-7R  
16Kx16  
MEMORY  
ARRAY  
(BANK 1)  
A13L  
A13R  
ADDRESS  
DECODE  
ADDRESS  
DECODE  
(1)  
(1)  
A0L  
A0R  
MUX  
BA1R  
BA0R  
BA1L  
BA0L  
BANK  
DECODE  
BANK  
DECODE  
MUX  
16Kx16  
MEMORY  
ARRAY  
(BANK 3)  
MUX  
(2)  
BKSEL3  
BKSEL0  
BANK  
SELECT  
(2)  
(1)  
(1)  
(1)  
(1)  
A5R  
A0R  
A5L  
A0L  
MAILBOX  
INTERRUPT  
LOGIC  
LBR/UBR  
OER  
LBL/UBL  
OEL  
R/WR  
CER  
R/WL  
CEL  
MBSELL  
INTL  
MBSELR  
INTR  
3592 drw 01  
NOTES:  
1. The first six address pins for each port serve dual functions. When MBSEL = VIH, the pins serve as memory address inputs. When MBSEL = VIL, the pins  
serve as mailbox address inputs.  
2. Each bank has an input pin assigned that allows the user to toggle the assignment of that bank between the two ports. Refer to Truth Table I for  
more details.  
MAY 2000  
1
DSC 3592/7  
©2000IntegratedDeviceTechnology,Inc.  

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