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IDT707288L25PF8 PDF预览

IDT707288L25PF8

更新时间: 2024-11-14 21:18:07
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
16页 132K
描述
Dual-Port SRAM, 64KX16, 25ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM, TQFP-100

IDT707288L25PF8 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:14 X 14 MM, 1.40 MM, TQFP-100
针数:100Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.32.00.41
风险等级:5.92最长访问时间:25 ns
其他特性:AUTOMATIC POWER-DOWN; LOW POWER STANDBY MODE; INTERRUPT FLAGI/O 类型:COMMON
JESD-30 代码:S-PQFP-G100JESD-609代码:e0
长度:14 mm内存密度:1048576 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:16
湿度敏感等级:3功能数量:1
端口数量:2端子数量:100
字数:65536 words字数代码:64000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:64KX16
输出特性:3-STATE可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装等效代码:QFP100,.63SQ,20封装形状:SQUARE
封装形式:FLATPACK并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:5 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.005 A最小待机电流:4.5 V
子类别:SRAMs最大压摆率:0.28 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:20宽度:14 mm
Base Number Matches:1

IDT707288L25PF8 数据手册

 浏览型号IDT707288L25PF8的Datasheet PDF文件第2页浏览型号IDT707288L25PF8的Datasheet PDF文件第3页浏览型号IDT707288L25PF8的Datasheet PDF文件第4页浏览型号IDT707288L25PF8的Datasheet PDF文件第5页浏览型号IDT707288L25PF8的Datasheet PDF文件第6页浏览型号IDT707288L25PF8的Datasheet PDF文件第7页 
HIGH-SPEED  
IDT707288S/L  
64K x 16 BANK-SWITCHABLE  
DUAL-PORTED SRAM WITH  
EXTERNAL BANK SELECTS  
Features  
64K x 16 Bank-Switchable Dual-Ported SRAM Architecture  
processor communications; interrupt option  
– Four independent 16K x 16 banks  
Interrupt flags with programmable masking  
Dual Chip Enables allow for depth expansion without  
external logic  
UB and LB are available for x8 or x16 bus matching  
TTL-compatible, single 5V (±10%) power supply  
Available in a 100-pin Thin Quad Flatpack (14mm x 14mm)  
– 1 Megabit of memory on chip  
Fast asynchronous address-to-data access time: 15ns  
User-controlled input pins included for bank selects  
Independent port controls with asynchronous address &  
data busses  
Four 16-bit mailboxes available to each port for inter-  
FunctionalBlockDiagram  
MUX  
R/WL  
R/WR  
CE0L  
16Kx16  
MEMORY  
ARRAY  
0R  
CE  
CONTROL  
LOGIC  
CONTROL  
LOGIC  
CE1L  
UBL  
LBL  
CE1R  
UBR  
LBR  
(BANK 0)  
OER  
OEL  
MUX  
MUX  
I/O  
CONTROL  
I/O  
CONTROL  
I/O8L-15L  
I/O0L-7L  
I/O8R-15R  
I/O0R-7R  
16Kx16  
MEMORY  
ARRAY  
(BANK 1)  
A13L  
A13R  
ADDRESS  
DECODE  
ADDRESS  
DECODE  
(1)  
(1)  
A0L  
A0R  
MUX  
BA1R  
BA0R  
BA1L  
BA0L  
BANK  
DECODE  
BANK  
DECODE  
MUX  
16Kx16  
MEMORY  
ARRAY  
(BANK 3)  
MUX  
(2)  
BKSEL3  
BKSEL0  
BANK  
SELECT  
(2)  
(1)  
(1)  
(1)  
(1)  
A5R  
A0R  
A5L  
A0L  
MAILBOX  
INTERRUPT  
LOGIC  
LBR/UBR  
OER  
LBL/UBL  
OEL  
R/WR  
CER  
R/WL  
CEL  
MBSELL  
INTL  
MBSELR  
INTR  
3592 drw 01  
NOTES:  
1. The first six address pins for each port serve dual functions. When MBSEL = VIH, the pins serve as memory address inputs. When MBSEL = VIL, the pins  
serve as mailbox address inputs.  
2. Each bank has an input pin assigned that allows the user to toggle the assignment of that bank between the two ports. Refer to Truth Table I for  
more details.  
MAY 2000  
1
DSC 3592/7  
©2000IntegratedDeviceTechnology,Inc.  

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