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IDT707288L PDF预览

IDT707288L

更新时间: 2024-09-25 22:57:19
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器
页数 文件大小 规格书
6页 69K
描述
HIGH-SPEED 64K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS

IDT707288L 数据手册

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HIGH-SPEED  
ADVANCED  
IDT707288S/L  
64K x 16 BANK-SWITCHABLE  
DUAL-PORTED SRAM WITH  
EXTERNAL BANK SELECTS  
Integrated Device Technology, Inc.  
FEATURES:  
• 64K x 16 Bank-Switchable Dual-Ported SRAM Architecture  
- Four independent 16K x 16 banks  
- 1 Megabit of memory on chip  
• Fast asynchronous address-to-data access time: 20ns  
• User-controlled input pins included for bank selects  
DESCRIPTION:  
The IDT707288 is a high-speed 64K x 16 (1M bit) Bank-  
Switchable Dual-Ported SRAM organized into four indepen-  
dent 16K x 16 banks. The device has two independent ports  
with separate controls, addresses, and I/O pins for each port,  
allowing each port to asynchronously access any 16K x 16  
• Independent port controls with asynchronous address & memory block not already accessed by the other port. Ac-  
data busses  
cesses by the ports into specific banks are controlled via bank  
select pin inputs under the user's control. Mailboxes are  
provided to allow inter-processor communications. Interrupts  
are provided to indicate mailbox writes have occurred. An  
automatic power down feature controlled by the chip enables  
(CE0 and CE1) permits the on-chip circuitry of each port to  
• Four 16-bit mailboxes available to each port for inter-  
processor communications; interrupt option  
• Interrupt flags with programmable masking  
• Dual Chip Enables allow for depth expansion without  
external logic  
• UB and LB are available for bus matching to x8 or x16 enter a very low standby power mode and allows fast depth  
busses; also support very fast banking  
expansion.  
• TTL-compatible, single 5V (±10%) power supply  
The IDT707288 offers a maximum address-to-data access  
• Available in a 100-pin Thin Quad Plastic Flatpack (TQFP) time as fast as 20ns, while typically operating on only 900mW  
and a 108-pin ceramic Pin Grid Array (PGA)  
of power, and is available in a 100-pin Thin Quad Plastic  
Flatpack (TQFP)anda108-pinceramicPinGridArray(PGA).  
FUNCTIONAL BLOCK DIAGRAM  
MUX  
R/  
L
R/  
R
16Kx16  
MEMORY  
ARRAY  
0L  
0R  
CONTROL  
LOGIC  
CONTROL  
LOGIC  
CE1L  
CE1R  
L
L
L
R
(BANK 0)  
R
R
MUX  
MUX  
I/O  
CONTROL  
I/O  
CONTROL  
I/O8L-15L  
I/O0L-7L  
I/O8R-15R  
I/O0R-7R  
16Kx16  
MEMORY  
ARRAY  
(BANK 1)  
A
13L  
A
13R  
ADDRESS  
DECODE  
ADDRESS  
DECODE  
(1)  
(1)  
0R  
A0L  
A
MUX  
BA1R  
BA0R  
BA1L  
BA0L  
BANK  
DECODE  
BANK  
DECODE  
MUX  
16Kx16  
MEMORY  
ARRAY  
(BANK 3)  
MUX  
(2)  
(2)  
BKSEL  
BKSEL  
3
0
BANK  
SELECT  
(1)  
(1)  
(1)  
(1)  
A
5R  
A
5L  
A0R  
A0L  
MAILBOX  
INTERRUPT  
LOGIC  
R/  
R
L/  
L
L
L
L
R
R/  
R
R/  
R
L
L
R
3592 drw 01  
R
NOTES:  
1. The first six address pins for each port serve dual functions. When MBSEL = VIH, the pins serve as memory address inputs. When MBSEL = VIL, the pins  
serve as mailbox address inputs.  
2. Each bank has an input pin assigned that allows the user to toggle the assignment of that bank between the two ports. Refer to Table I for more details.  
The IDT logo is a registered trademark of Integrated Device Technology  
COMMERCIAL TEMPERATURE RANGE  
OCTOBER 1996  
©1996 Integrated Device Technology, Inc.  
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.  
DSC-3592/-  
1
6.29  

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