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IDT7034S20PF9 PDF预览

IDT7034S20PF9

更新时间: 2024-11-28 15:34:43
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
19页 154K
描述
Dual-Port SRAM, 4KX18, 20ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100

IDT7034S20PF9 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:14 X 14 MM, 1.40 MM HEIGHT, TQFP-100针数:100
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.92
最长访问时间:20 nsJESD-30 代码:S-PQFP-G100
JESD-609代码:e0长度:14 mm
内存密度:73728 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:18湿度敏感等级:3
功能数量:1端子数量:100
字数:4096 words字数代码:4000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:4KX18
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):240
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:20宽度:14 mm
Base Number Matches:1

IDT7034S20PF9 数据手册

 浏览型号IDT7034S20PF9的Datasheet PDF文件第2页浏览型号IDT7034S20PF9的Datasheet PDF文件第3页浏览型号IDT7034S20PF9的Datasheet PDF文件第4页浏览型号IDT7034S20PF9的Datasheet PDF文件第5页浏览型号IDT7034S20PF9的Datasheet PDF文件第6页浏览型号IDT7034S20PF9的Datasheet PDF文件第7页 
IDT7034S/L  
HIGH-SPEED  
4K x 18 DUAL-PORT  
STATIC RAM  
Features:  
using the Master/Slave select when cascading more than  
one device  
M/S = H for BUSY output flag on Master  
M/S = L for BUSY input on Slave  
Interrupt Flag  
On-chip port arbitration logic  
True Dual-Ported memory cells which allow simultaneous  
reads of the same memory location  
High-speed access  
– Commercial:15/20ns (max.)  
Industrial:20ns (max.)  
Low-power operation  
Full on-chip hardware support of semaphore signaling  
between ports  
IDT7034S  
Active:850mW(typ.)  
Standby: 5mW (typ.)  
IDT7034L  
Fully asynchronous operation from either port  
Battery backup operation2V data retention  
TTL-compatible, single 5V (±10%) power supply  
Available in 100-pin Thin Quad Flatpack  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
Active:850mW(typ.)  
Standby: 1mW (typ.)  
Separate upper-byte and lower-byte control for multi-  
plexed bus compatibility  
IDT7034 easily expands data bus width to 36 bits or more  
Functional Block Diagram  
R/  
W
L
L
R/  
W
R
UB  
UB  
R
LB  
CE  
OE  
L
LB  
CE  
OE  
R
R
L
L
R
I/O9L-I/O17L  
I/O0L-I/O8L  
I/O9R-I/O17R  
.
I/O  
Control  
I/O  
Control  
I/O0R-I/O8R  
(1,2)  
BUSY (1,2)  
L
BUSY  
R
A
11L  
A
11R  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A
0L  
A
0R  
13  
13  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE  
OE  
R/  
R
CE  
OE  
R/  
L
R
L
W
R
WL  
SEM  
R
SEM  
L
(2)  
(2)  
INTR  
M/S  
INTL  
4089 drw 01  
NOTES:  
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.  
2. BUSY outputs and INT outputs are non-tri-stated push-pull.  
AUGUST 2001  
1
DSC 4089/8  
©2001IntegratedDeviceTechnology,Inc.  

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