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IDT7035S20PF9 PDF预览

IDT7035S20PF9

更新时间: 2024-10-28 14:31:15
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
19页 165K
描述
Dual-Port SRAM, 8KX8, 20ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100

IDT7035S20PF9 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LFQFP,针数:100
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.33
最长访问时间:20 ns其他特性:SEMAPHORE; AUTOMATIC POWER-DOWN
JESD-30 代码:S-PQFP-G100JESD-609代码:e0
长度:14 mm内存密度:65536 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:8
湿度敏感等级:3功能数量:1
端子数量:100字数:8192 words
字数代码:8000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:8KX8封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):240认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
宽度:14 mmBase Number Matches:1

IDT7035S20PF9 数据手册

 浏览型号IDT7035S20PF9的Datasheet PDF文件第2页浏览型号IDT7035S20PF9的Datasheet PDF文件第3页浏览型号IDT7035S20PF9的Datasheet PDF文件第4页浏览型号IDT7035S20PF9的Datasheet PDF文件第5页浏览型号IDT7035S20PF9的Datasheet PDF文件第6页浏览型号IDT7035S20PF9的Datasheet PDF文件第7页 
HIGH-SPEED  
8K x 18 DUAL-PORT  
STATIC RAM  
IDT7035S/L  
Features  
True Dual-Ported memory cells which allow simultaneous  
using the Master/Slave select when cascading more than  
one device  
M/S = H for BUSY output flag on Master  
M/S = L for BUSY input on Slave  
Interrupt Flag  
On-chip port arbitration logic  
reads of the same memory location  
High-speed access  
– Commercial:15/20ns (max.)  
Industrial:20ns (max.)  
Low-power operation  
IDT7035S  
Full on-chip hardware support of semaphore signaling  
between ports  
Active:800mW(typ.)  
Standby: 5mW (typ.)  
IDT7035L  
Fully asynchronous operation from either port  
Battery backup operation2V data retention  
TTL-compatible, single 5V (±10%) power supply  
Available in 100-pin Thin Quad Flatpack  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
Active:800mW(typ.)  
Standby: 1mW (typ.)  
Separate upper-byte and lower-byte control for multiplexed  
bus compatibility  
IDT7035 easily expands data bus width to 36 bits or more  
FunctionalBlockDiagram  
R/WL  
R/  
W
R
R
UBL  
UB  
LB  
CE  
OE  
L
L
L
LB  
CE  
OE  
R
R
R
I/O9L-I/O17L  
I/O0L-I/O8L  
I/O9R-I/O17R  
I/O  
Control  
I/O  
Control  
I/O0R-I/O8R  
(1,2)  
L
(1,2)  
R
BUSY  
BUSY  
A
12L  
A
12R  
0R  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A
0L  
A
13  
13  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE  
OE  
L
L
CE  
OE  
R/  
R
R
R/WL  
W
R
SEM  
R
SEM  
INTL  
L
(2)  
(2)  
INTR  
M/S  
4088 drw 01  
NOTES:  
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.  
2. BUSY outputs and INT outputs are non-tri-stated push-pull.  
AUGUST 2001  
1
DSC 4088/8  
©2001IntegratedDeviceTechnology,Inc.  

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